Semiconductor device and memory device

ABSTRACT

A semiconductor device that can measure a minute current. The semiconductor device includes a first transistor, a second transistor, a node, and a capacitor. The first transistor includes an oxide semiconductor in a channel formation region. The node is electrically connected to a gate of the second transistor and a first terminal of the capacitor. The node is brought into an electrically floating state by turning off the first transistor after a potential V 0  is supplied. Change in a potential V FN  of the node over time is expressed by Formula (1). In Formula (1), t is elapsed time after the node is brought into the electrically floating state, τ is a constant with a unit of time, and β is a constant greater than or equal to 0.4 and less than or equal to 0.6. 
     
       
         
           
             
               
                 
                   
                     
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BACKGROUND OF THE INVENTION 1. Field of the Invention

The present invention relates to a semiconductor device and a memorydevice.

The present invention relates to an object, a method, or a manufacturingmethod. In addition, the present invention relates to a process, amachine, manufacture, or a composition of matter. One embodiment of thepresent invention relates to a semiconductor device, a display device, alight-emitting device, a power storage device, a memory device, animaging device, a method for driving them, or a method for manufacturingthem. In particular, one embodiment of the present invention relates toa semiconductor device, a display device, or a light-emitting deviceeach including an oxide semiconductor.

In this specification and the like, a semiconductor device generallymeans a device that can function by utilizing semiconductorcharacteristics. In some cases, a display device, an electro-opticaldevice, a semiconductor circuit, or an electronic device includes asemiconductor device.

2. Description of the Related Art

Attention has been focused on a technique for forming a transistor usinga semiconductor thin film formed over a substrate having an insulatingsurface (also referred to as thin film transistor (TFT)). Suchtransistors are applied to a wide range of electronic devices such as anintegrated circuit (IC) and an image display device (display device). Asemiconductor material typified by silicon is widely known as a materialfor a semiconductor thin film that can be used for a transistor, and anoxide semiconductor has been attracting attention as well. For example,a technique for manufacturing a transistor using zinc oxide or anIn—Ga—Zn oxide semiconductor is disclosed (see Patent Document 1).

The off-state current of a transistor using an oxide semiconductor isextremely low. Patent Documents 2 and 3 each disclose a nonvolatilememory device utilizing the above feature by including an oxidesemiconductor transistor. Such a memory device does not have a limit onthe number of times of data rewriting and consumes low power.

REFERENCE Patent Document [Patent Document 1] Japanese Published PatentApplication No. 2007-123861 [Patent Document 2] Japanese PublishedPatent Application No. 2012-256400 [Patent Document 3] JapanesePublished Patent Application No. 2015-008030 SUMMARY OF THE INVENTION

In the memory devices including oxide semiconductors disclosed in PatentDocuments 2 and 3, to accurately estimate data retention time, it isnecessary to accurately estimate an off-state current of the oxidesemiconductor transistor, however, the off-state current of the oxidesemiconductor transistor is lower than the detection limit of ameasurement device in many cases and difficult to directly measure.

An object of one embodiment of the present invention is to provide asemiconductor device that can measure a minute current. Another objectof one embodiment of the present invention is to provide a memory devicethat can retain data for a long time. Another object of one embodimentof the present invention is to provide a semiconductor device that canmeasure a minute current and retain data for a long time. Another objectof one embodiment of the present invention is to provide a novelsemiconductor device.

Note that the description of a plurality of objects does not mutuallypreclude the existence. One embodiment of the present invention does notnecessarily achieve all the objects listed above. Objects other thanthose listed above are apparent from the description of thespecification, drawings, and claims, and also such objects could be anobject of one embodiment of the present invention.

One embodiment of the present invention is a semiconductor device thatincludes a first transistor, a second transistor, a node, and acapacitor. The first transistor includes an oxide semiconductor in achannel formation region. The node is electrically connected to a gateof the second transistor and a first terminal of the capacitor. The nodeis supplied with a potential V₀ through the first transistor. The nodeis brought into an electrically floating state by turning off the firsttransistor after the potential V₀ is supplied. Change in a potentialV_(FN) of the node over time is expressed by Formula (1). In Formula(1), t is elapsed time after the node is brought into the electricallyfloating state, τ is a constant with a unit of time, and β is a constantgreater than or equal to 0.4 and less than or equal to 0.6.

$\begin{matrix}\left\lbrack {{Formula}\mspace{14mu} 1} \right\rbrack & \; \\{{V_{FN}(t)} = {V_{0} \times e^{- {(\frac{t}{\tau})}^{\beta}}}} & (1)\end{matrix}$

One embodiment of the present invention is a semiconductor device thatincludes a first transistor, a second transistor, a third transistor, anode, and a capacitor. The first transistor includes an oxidesemiconductor in a channel formation region. The node is electricallyconnected to a gate of the second transistor and a first terminal of thecapacitor. One of a source and a drain of the third transistor iselectrically connected to one of a source and a drain of the secondtransistor. The node is supplied with a potential V₀ through the firsttransistor. The node is brought into an electrically floating state byturning off the first transistor after the potential V₀ is supplied.Change in a potential V_(FN) of the node over time is expressed byFormula (1). In Formula (1), t is elapsed time after the node is broughtinto the electrically floating state, τ is a constant with a unit oftime, and β is a constant greater than or equal to 0.4 and less than orequal to 0.6.

In the above embodiments, τ preferably follows the Arrhenius equation.

In the above embodiments, an off-state current of the first transistorcan be measured by measuring change in the potential V_(FN) over time.

One embodiment of the present invention is a memory device that includesthe semiconductor device in any of the above embodiments.

In the above memory device, data can be retained for 10 years or longerat 85° C.

In the above memory device, data can be retained for 100 years or longerat 85° C.

Another embodiment of the present invention is an electronic device thatincludes the above memory device and at least one of a microphone, aspeaker, a display portion, and an operation key.

In this specification and the like, terms for describing arrangement,such as “over” and “under,” are used for convenience to indicate apositional relation between components with reference to drawings. Thepositional relation between components is changed as appropriate inaccordance with the direction in which each component is described.Therefore, terms for describing arrangement are not limited to the termsused in the description in the specification, and can be appropriatelyreworded depending on the situation.

In this specification and the like, components are classified on thebasis of the functions, and shown as blocks independent of one anotherin block diagrams. However, in an actual circuit or the like, it may bedifficult to separate components on the basis of the functions, so thatone circuit may be associated with a plurality of functions and severalcircuits may be associated with one function. Therefore, thesegmentation of a block in the block diagrams is not limited by any ofthe components described in the specification, and can be differentlydetermined as appropriate depending on the situation.

In the drawings, the size, the layer thickness, or the region hasarbitrary magnitude for convenience for the description. Therefore, thescale is not necessarily limited to that illustrated in the drawings.Note that the drawings are schematically illustrated for clarity, andshapes or values are not limited to those illustrated in the drawings.For example, the following can be included: variation in signal,voltage, or current due to noise or difference in timing.

In this specification and the like, in description of connections of atransistor, description of “one of a source and a drain” (or a firstelectrode or a first terminal), and “the other of the source and thedrain” (or a second electrode or a second terminal) are used. This isbecause a source and a drain of a transistor are interchangeabledepending on the structure, operation conditions, or the like of thetransistor. Note that the source or the drain of the transistor can alsobe referred to as a source (or drain) terminal, a source (or drain)electrode, or the like as appropriate depending on the situation.

In addition, in this specification and the like, the term such as an“electrode” or a “wiring” does not limit the function of a component.For example, an “electrode” is used as part of a “wiring” in some cases,and vice versa. Further, the term “electrode” or “wiring” can also meana combination of a plurality of “electrodes” or “wirings” formed in anintegrated manner.

In this specification and the like, the terms “voltage” and “potential”are interchangeable in appropriate cases. The term “voltage” refers to apotential difference between a given potential and a referencepotential. When the reference potential is a ground potential, the term“voltage” can be replaced with the term “potential.” The groundpotential does not necessarily mean 0 V. Note that a potential isrelative, and a potential supplied to wirings or the like may be changeddepending on a reference potential.

In this specification and the like, the terms “film,” “layer,” and thelike can be interchanged with each other depending on the case orcircumstances. For example, the term “conductive layer” can be changedinto the term “conductive film” in some cases. The term “insulatingfilm” can be changed into the term “insulating layer” in some cases.

In this specification and the like, a switch is an element that isbrought into a conduction state or a non-conduction state (is turned onor off) to determine whether to have a current flow therethrough or not.Alternatively, the switch is an element having a function of selectingand changing a current path.

For example, an electrical switch, a mechanical switch, or the like canbe used as a switch. That is, any element can be used as a switch aslong as it can control a current, without limitation to a certainelement.

A transistor (e.g., a bipolar transistor or a MOS transistor), a diode(e.g., a PN diode, a PIN diode, a Schottky diode, ametal-insulator-metal (MIM) diode, a metal-insulator-semiconductor (MIS)diode, or a diode-connected transistor), or a logic circuit in whichsuch elements are combined can be used as an electrical switch.

When a transistor is used as a switch, an “on state” of the transistorrefers to a state in which a source and a drain of the transistor areelectrically short-circuited. Furthermore, an “off state” of thetransistor refers to a state in which the source and drain of thetransistor are electrically disconnected. Note that if the transistoroperates just as a switch, there is no particular limitation on thepolarity (conductivity type) of the transistor.

An example of a mechanical switch is a switch formed using a MEMS (microelectro mechanical systems) technology, such as a digital micromirrordevice (DMD). Such a switch includes an electrode which can be movedmechanically, and operates by controlling conduction and non-conductionin accordance with movement of the electrode.

For example, in this specification and the like, an explicit description“X and Y are connected” means that X and Y are electrically connected, Xand Y are functionally connected, and X and Y are directly connected.Accordingly, without limitation to a predetermined connection relation,for example, a connection relation shown in drawings or text, anotherconnection relation is included in the drawings or the text.

Here, X and Y each denote an object (e.g., a device, an element, acircuit, a wiring, an electrode, a terminal, a conductive film, or alayer).

Examples of the case where X and Y are directly connected include thecase where an element that allows an electrical connection between X andY (e.g., a switch, a transistor, a capacitor, an inductor, a resistor, adiode, a display element, a light-emitting element, and a load) is notconnected between X and Y, that is, the case where X and Y are connectedwithout the element that allows the electrical connection between X andY provided therebetween.

For example, in the case where X and Y are electrically connected, oneor more elements that enable electrical connection between X and Y(e.g., a switch, a transistor, a capacitor, an inductor, a resistor, adiode, a display element, a light-emitting element, and a load) can beconnected between X and Y. A switch is controlled to be on or off. Thatis, a switch is conducting or not conducting (is turned on or off) todetermine whether a current flows therethrough or not. Alternatively,the switch has a function of selecting and changing a current path. Notethat the case where X and Y are electrically connected includes the casewhere X and Y are directly connected.

For example, in the case where X and Y are functionally connected, oneor more circuits that enable functional connection between X and Y(e.g., a logic circuit such as an inverter, a NAND circuit, or a NORcircuit; a signal converter circuit such as a DA converter circuit, anAD converter circuit, or a gamma correction circuit; a potential levelconverter circuit such as a power supply circuit (e.g., a step-upcircuit and a step-down circuit) or a level shifter circuit for changingthe potential level of a signal, a voltage source; a current source; aswitching circuit; an amplifier circuit such as a circuit that canincrease signal amplitude, the amount of a current, or the like, anoperational amplifier, a differential amplifier circuit, a sourcefollower circuit, or a buffer circuit; a signal generation circuit; amemory circuit; and/or a control circuit) can be connected between X andY. Note that for example, in the case where a signal output from X istransmitted to Y even when another circuit is interposed between X andY, X and Y are functionally connected. Note that the case where X and Yare functionally connected includes the case where X and Y are directlyconnected and X and Y are electrically connected.

Note that in this specification and the like, an explicit description “Xand Y are electrically connected” means that X and Y are electricallyconnected (i.e., the case where X and Y are connected with anotherelement or another circuit provided therebetween), X and Y arefunctionally connected (i.e., the case where X and Y are functionallyconnected with another circuit provided therebetween), and X and Y aredirectly connected (i.e., the case where X and Y are connected withoutanother element or another circuit provided therebetween). That is, inthis specification and the like, the explicit description “X and Y areelectrically connected” is the same as the explicit description “X and Yare connected.”

Note that for example, the case where a source (or a first terminal orthe like) of a transistor is electrically connected to X through (or notthrough) Z1 and a drain (or a second terminal or the like) of thetransistor is electrically connected to Y through (or not through) Z2,or the case where a source (or a first terminal or the like) of atransistor is directly connected to a part of Z1 and another part of Z1is directly connected to X while a drain (or a second terminal or thelike) of the transistor is directly connected to a part of Z2 andanother part of Z2 is directly connected to Y, can be expressed by usingany of the following expressions.

The expressions include, for example, “X, Y, a source (or a firstterminal or the like) of a transistor, and a drain (or a second terminalor the like) of the transistor are electrically connected to each other,and X, the source (or the first terminal or the like) of the transistor,the drain (or the second terminal or the like) of the transistor, and Yare electrically connected to each other in this order,” “a source (or afirst terminal or the like) of a transistor is electrically connected toX, a drain (or a second terminal or the like) of the transistor iselectrically connected to Y, and X, the source (or the first terminal orthe like) of the transistor, the drain (or the second terminal or thelike) of the transistor, and Y are electrically connected to each otherin this order,” and “X is electrically connected to Y through a source(or a first terminal or the like) and a drain (or a second terminal orthe like) of a transistor, and X, the source (or the first terminal orthe like) of the transistor, the drain (or the second terminal or thelike) of the transistor, and Y are provided to be connected in thisorder.” When the connection order in a circuit configuration is definedby an expression similar to the above examples, a source (or a firstterminal or the like) and a drain (or a second terminal or the like) ofa transistor can be distinguished from each other to specify thetechnical scope.

Other examples of the expressions include, “a source (or a firstterminal or the like) of a transistor is electrically connected to Xthrough at least a first connection path, the first connection path doesnot include a second connection path, the second connection path is apath between the source (or the first terminal or the like) of thetransistor and a drain (or a second terminal or the like) of thetransistor, Z1 is on the first connection path, the drain (or the secondterminal or the like) of the transistor is electrically connected to Ythrough at least a third connection path, the third connection path doesnot include the second connection path, and Z2 is on the thirdconnection path.” Other examples of the expressions also include “asource (or a first terminal or the like) of a transistor is electricallyconnected to X through at least Z1 on a first connection path, the firstconnection path does not include a second connection path, the secondconnection path includes a connection path through the transistor, adrain (or a second terminal or the like) of the transistor iselectrically connected to Y through at least Z2 on a third connectionpath, and the third connection path does not include the secondconnection path,” and “a source (or a first terminal or the like) of atransistor is electrically connected to X through at least Z1 on a firstelectrical path, the first electrical path does not include a secondelectrical path, the second electrical path is an electrical path fromthe source (or the first terminal or the like) of the transistor to adrain (or a second terminal or the like) of the transistor, the drain(or the second terminal or the like) of the transistor is electricallyconnected to Y through at least Z2 on a third electrical path, the thirdelectrical path does not include a fourth electrical path, and thefourth electrical path is an electrical path from the drain (or thesecond terminal or the like) of the transistor to the source (or thefirst terminal or the like) of the transistor” When the connection pathin a circuit configuration is defined by an expression similar to theabove examples, a source (or a first terminal or the like) and a drain(or a second terminal or the like) of a transistor can be distinguishedfrom each other to specify the technical scope.

Note that these expressions are only examples and one embodiment of thepresent invention is not limited to the expressions. Here, X, Y, Z1, andZ2 each denote an object (e.g., a device, an element, a circuit, awiring, an electrode, a terminal, a conductive film, and a layer).

Even when independent components are electrically connected to eachother in a circuit diagram, one component has functions of a pluralityof components in some cases. For example, when part of a wiring alsofunctions as an electrode, one conductive film functions as the wiringand the electrode. Thus, “electrical connection” in this specificationincludes in its category such a case where one conductive film hasfunctions of a plurality of components.

Unless otherwise specified, an off-state current in this specificationrefers to a drain current of a transistor in an off state. Unlessotherwise specified, the off state of an n-channel transistor means thata difference between gate voltage and source voltage (V_(gs)) is lowerthan the threshold voltage (V_(th)), and the off state of a p-channeltransistor means that V_(gs) is higher than V_(th). For example, theoff-state current of an n-channel transistor sometimes refers to a draincurrent that flows when V_(gs) is lower than V_(th). The off-statecurrent of a transistor depends on V_(gs) in some cases. Thus, “theoff-state current of a transistor is lower than or equal to 10⁻²¹ A”means “there is V_(gs) with which the off-state current of a transistorbecomes lower than or equal to 10⁻²¹ A” in some cases.

The off-state current of a transistor depends on voltage V_(ds) betweenits drain and source in some cases. Unless otherwise specified, theoff-state current in this specification might be an off-state current atV_(ds) with an absolute value of 0.1 V, 0.8 V, 1 V, 1.2 V, 1.8 V, 2.5 V,3 V, 3.3 V 10 V, 12 V, 16 V, or 20 V. Alternatively, the off-statecurrent might be V_(ds) used in the semiconductor device or the likeincluding the transistor.

Furthermore, in the present specification, any of the embodiments andthe examples below can be combined as appropriate. In the case wheresome structural examples are given in one embodiment or example, any ofthe structure examples can be combined as appropriate.

One embodiment of the present invention can provide a semiconductordevice that can measure a minute current. One embodiment of the presentinvention can provide a memory device that can retain data for a longtime. One embodiment of the present invention can provide asemiconductor device that can measure a minute current and retain datafor a long time. One embodiment of the present invention can provide anovel semiconductor device.

Note that the description of these effects does not disturb theexistence of other effects. One embodiment of the present invention doesnot necessarily have all the effects listed above. Other effects will beapparent from and can be derived from the description of thespecification, the drawings, the claims, and the like.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B are circuit diagrams showing structure examples ofmemory devices.

FIG. 2 is a circuit diagram showing an example of a characteristicsevaluation circuit.

FIG. 3 is a timing chart showing an operation example of acharacteristics evaluation circuit.

FIG. 4 is a circuit diagram showing an example of a characteristicsevaluation circuit.

FIG. 5 illustrates an example of a measurement environment.

FIG. 6 is a circuit diagram showing an example of a memory cell.

FIG. 7 is a timing chart illustrating an operation example of a memorycell.

FIG. 8 is a block diagram showing an example of a memory device.

FIGS. 9A and 9B are circuit diagrams each showing an example of a memorycell.

FIGS. 10A and 10B are circuit diagrams each showing an example of amemory cell.

FIG. 11A is a top view and FIGS. 11B to 11D are cross-sectional viewsillustrating a structure example of a transistor.

FIG. 12A is a cross-sectional view and FIG. 12B is an energy banddiagram illustrating a structure example of a transistor.

FIG. 13A is a top view and FIGS. 13B to 13D are cross-sectional viewsillustrating a structure example of a transistor.

FIG. 14A is a top view and FIGS. 14B to 14D are cross-sectional viewsillustrating a structure example of a transistor.

FIG. 15 is a cross-sectional view illustrating a structure example of atransistor.

FIG. 16 is a cross-sectional view illustrating a structure example of atransistor.

FIG. 17 is a cross-sectional view illustrating a structure example of atransistor.

FIG. 18A is a top view and FIG. 18B is a cross-sectional viewillustrating a structure example of a transistor.

FIG. 19 is a block diagram showing an example of a CPU.

FIGS. 20A to 20F each illustrate an example of an electronic device.

FIGS. 21A to 21F each illustrate an example of an RF tag.

FIG. 22 shows a cross-sectional STEM image of a prototype circuit.

FIG. 23 shows V_(g)-I_(d) characteristics of a prototype transistor.

FIG. 24 is a graph showing change in a potential V_(FN) of a retentionnode of a prototype circuit over time.

FIG. 25 is a graph showing change in a potential V_(FN) of a retentionnode of a prototype circuit over time, a stretched exponential function,and an exponential function.

FIG. 26 is a graph showing τ and β of a stretched exponential functionas a function of a potential V_(OFF) in a prototype circuit.

FIG. 27 is a graph showing a current I_(OFF) as a function of apotential V_(OFF) in a prototype circuit.

FIG. 28 is a graph showing an Arrhenius plot of τ of a stretchedexponential function in a prototype circuit.

FIGS. 29A and 29B show cross-sectional STEM images of a prototypetransistor.

FIG. 30 is a graph showing change in a potential V_(FN) of a retentionnode of a prototype circuit over time and a stretched exponentialfunction.

FIG. 31 is a graph showing results of a +DBTS test for a prototypetransistor.

FIG. 32 shows a cross-sectional STEM image of a prototype transistor.

FIG. 33 is a graph showing an off-state current of a prototypetransistor.

FIG. 34 is a cross-sectional view illustrating a device structure of aprototype circuit.

FIG. 35 shows an optical micrograph of a prototype circuit.

FIG. 36 shows V_(g)-I_(d) characteristics of a prototype transistor.

FIGS. 37A to 37D are graphs each showing a bit error ratio as a functionof data retention time in a prototype circuit.

FIG. 38 is a graph showing an Arrhenius plot of data retention time of aprototype circuit.

FIG. 39 shows V_(g)-I_(d) characteristics of a prototype transistor.

FIG. 40 is a graph showing a bit error ratio as a function of dataretention time in a prototype circuit.

FIG. 41A is a circuit diagram of a prototype TEG, FIG. 41B is a timingchart of operation of a prototype TEG, and FIG. 41C is a circuit diagramof a cell array including the TEGs.

FIGS. 42A and 42B show histograms of a potential V_(SL) obtained bymeasurement performed on prototype TEGs.

FIG. 43 shows histograms of a potential V_(SL) obtained by measurementperformed on prototype TEGs.

FIG. 44A shows 3σ of a potential V_(SL) as a function of a potentialV_(WL), and FIG. 44B shows an average value of a potential V_(SL) as afunction of a potential V_(WL).

FIGS. 45A and 45B show 3σ of a potential V_(SL) of TEGs formed over onesubstrate.

FIG. 46 shows a histogram of a potential V_(SL) obtained by measurementperformed on TEGs arranged in a column direction.

FIG. 47 shows an optical micrograph of a prototype chip.

FIG. 48 shows a histogram of a potential V_(FN) of a prototype memorydevice.

FIGS. 49A and 49B are graphs each showing a bit error ratio as afunction of data retention time in a prototype memory device.

FIG. 50 shows a histogram of a potential V_(FN) of a prototype memorydevice.

FIGS. 51A to 51C each show a histogram of a potential V_(FN) of aprototype memory device.

FIG. 52 shows a histogram of a potential V_(FN) of a prototype memorydevice.

FIG. 53 shows histograms of a potential V_(SL) of a prototype memorydevice.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, embodiments will be described with reference to drawings.However, the embodiments can be implemented with various modes. It willbe readily appreciated by those skilled in the art that modes anddetails can be changed in various ways without departing from the spiritand scope of the present invention. Thus, the present invention shouldnot be interpreted as being limited to the following description of theembodiments.

In the drawings, the size, the layer thickness, or the region isexaggerated for clarity in some cases. Therefore, embodiments of thepresent invention are not limited to such a scale. Note that drawingsare schematic views of ideal examples, and the embodiments of thepresent invention are not limited to the shape or the value illustratedin the drawings.

In this specification, a high power supply potential is referred to asan H level (or potential V_(DD)), and a low power supply potential isreferred to as an L level (or potential GND), in some cases.

Embodiment 1

In this embodiment, examples of a semiconductor device of one embodimentof the present invention are described with reference to drawings. Theconfiguration of a semiconductor device described below can be used asthe configurations of a memory device and a characteristics evaluationcircuit.

<<Circuit MC0>>

A circuit MC0 illustrated in FIG. 1A includes a transistor M0, atransistor M1, and a capacitor Cs.

A first terminal of the capacitor Cs, one of a source and a drain of thetransistor M0, and a gate of the transistor M1 are electricallyconnected to one another. Note that a node of the first terminal of thecapacitor Cs, one of the source and the drain of the transistor M0, andthe gate of the transistor M1 is called a node FN.

It is preferable that the transistor M0 be a transistor with a lowoff-state current. As an example of a transistor with a low off-statecurrent, a transistor including a wide band gap semiconductor, such as atransistor including an oxide semiconductor in a channel formationregion (an oxide semiconductor transistor), can be given.

Electric charge Q (data) is written in the node FN through thetransistor M0. By turning off the transistor M0 after writing of theelectric charge Q in the node FN, the node FN is brought into anelectrically floating state to retain the electric charge Q. When apotential difference is applied between a source and a drain of thetransistor M1 in this state and a current flowing in the transistor M1is measured, the electric charge Q written in the node FN can be read.

Because of having the above features, the circuit MC0 can be applied toa memory device.

The electric charge Q written in the node FN leaks out owing to a slightamount of an off-state current flowing in the transistor M0. As aresult, the potential of the node FN gradually decreases.

To examine the characteristics of retaining the electric charge Qwritten in the node FN, it is necessary to measure an off-state currentof the transistor M0; however, the off-state current of the transistorM0 is extremely low and difficult to directly measure. For example, whenthe transistor M0 is an oxide semiconductor transistor, an off-statecurrent of the transistor M0 is lower than the detection limit of ameasurement device in many cases.

Thus, a method as illustrated in FIG. 1A is effective, in which changein the potential of the node FN is measured using the value of a currentflowing in the transistor M1 to estimate the off-state current of thetransistor M0 from the change in the potential of the node FN. Thismethod is described below.

First, the transistor M0 is turned on and the node FN is supplied with apotential V₀.

Then, the transistor M0 is turned off to make the node FN electricallyfloating, and a potential difference is applied between the source andthe drain of the transistor M1. A current corresponding to the potentialdifference between the node FN and the source flows in the transistorM1. By reading the current, the potential of the node FN is measured.Hereinafter, the potential of the node FN is referred to as potentialV_(FN).

By regularly measuring the potential V_(FN), time-series data of thepotential V_(FN) (a graph in which the vertical axis represents thepotential VF and the horizontal axis represents elapsed time after thenode FN is brought into an electrically floating state) is made.

After the node FN is brought into an electrically floating state, owingto an off-state current flowing in the transistor M0, the potentialV_(FN) of the node FN decreases in accordance with a stretchedexponential function represented by Formula (2).

$\begin{matrix}\left\lbrack {{Formula}\mspace{14mu} 2} \right\rbrack & \; \\{{V_{FN}(t)} = {V_{0} \times e^{- {(\frac{t}{\tau})}^{\beta}}}} & (2)\end{matrix}$

In Formula (2), t is elapsed time after the node FN is brought into anelectrically floating state, τ is relaxation time and is a constant witha unit of time, β is a constant greater than or equal to 0 and less thanor equal to 1. In Formula (2), t is sometimes measurement time.

By fitting Formula (2) to the time-series data of the potential V_(FN)obtained by measurement, τ and β are determined.

The derivative of both sides of Formula (2) with respect to time givesFormula (3).

$\begin{matrix}\left\lbrack {{Formula}\mspace{14mu} 3} \right\rbrack & \; \\{\frac{{dV}_{FN}}{dt} = {{- \frac{V_{0} \times \beta}{\tau^{\beta}}} \times t^{\beta - 1} \times e^{- {(\frac{t}{\tau})}^{\beta}}}} & (3)\end{matrix}$

An off-state current I_(OFF) of the transistor M0, capacitance C_(S) ofthe capacitor Cs, and the potential V_(FN) of the node FN satisfy thefollowing relational expression.

$\begin{matrix}\left\lbrack {{Formula}\mspace{14mu} 4} \right\rbrack & \; \\{{I_{OFF}(t)} = {C_{S} \times \frac{{dV}_{FN}}{dt}}} & (4)\end{matrix}$

Substitution of Formula (3) into Formula (4) gives the followingformula.

$\begin{matrix}\left\lbrack {{Formula}\mspace{14mu} 5} \right\rbrack & \; \\{{I_{OFF}(t)} = {C_{S} \times \frac{V_{0} \times \beta}{\tau^{\beta}} \times t^{\beta - 1} \times e^{- {(\frac{t}{\tau})}^{\beta}}}} & (5)\end{matrix}$

When τ and β determined by fitting Formula (2) are substituted intoFormula (5), the off-state current of the transistor M0 can beestimated.

When the off-state current of the transistor M0 is low, β can be greaterthan or equal to 0.3 and less than or equal to 0.7, preferably greaterthan or equal to 0.4 and less than or equal to 0.6.

When the off-state current of the transistor M0 is low, τ is preferablygreater than or equal to 1×10⁷ seconds and less than or equal to 1×10¹⁰seconds, or greater than or equal to 1×10⁸ seconds and less than orequal to 1×10⁹ seconds at 85° C.

When the off-state current of the transistor M0 is low, τ follows theArrhenius equation.

Note that details about the values of β and τ are described later inExample 1.

The circuit MC0 may include a transistor M2 as in a circuit MC0 aillustrated in FIG. 1B. One of a source and a drain of the transistor M2is electrically connected to one of the source and the drain of thetransistor M1.

In the circuit MC0 a, the transistor M2 makes it possible to control thetiming of reading the electric charge in the node FN (the timing ofsupplying a current to the transistor M1).

By employing the above-described method, each of the circuit MC0 and thecircuit MC0 a can be used not only as a memory device but also as acharacteristics evaluation circuit. In the case where the circuits areused as characteristics evaluation circuits, the transistor M0 is atransistor under test (a device under test, DUT).

Note that more specific structure examples in which the circuit MC0 andthe circuit MC0 a are used for characteristics evaluation circuits aredescribed later in Embodiment 2.

More specific structure examples in which the circuit MC0 and thecircuit MC0 a are used for memory devices are described later inEmbodiment 3.

Embodiment 2

In this embodiment, more specific structure examples in which thecircuit MC0 and the circuit MC0 a described in Embodiment 1 are used ascharacteristics evaluation circuits are described.

<<Structure Example of Circuit MC1>>

A circuit MC1 in FIG. 2 includes the transistor M0, the transistor M1,the transistor M2, a transistor M3, the capacitor Cs, and an inverterINV. Note that the node of the first terminal of the capacitor Cs, oneof the source and the drain of the transistor M0, and the gate of thetransistor M1 is called the node FN.

The circuit MC1 is a characteristics evaluation circuit for measuringthe off-state current of the transistor M0, which is a transistor undertest. The circuit MC1 is the circuit MC0 a in FIG. 1B to which thetransistor M3 and the inverter INV are added.

The transistor M0 may have first and second gates. The first gate of thetransistor M0 is electrically connected to a terminal WWL_t, one of thesource and the drain of the transistor M0 is electrically connected tothe gate of the transistor M1 and the first terminal of the capacitorCs, the other of the source and the drain of the transistor M0 iselectrically connected to a terminal WBL_t, and the second gate of thetransistor M0 is electrically connected to a terminal BG_t. Note thatthe second gate of the transistor M0 and the terminal BG_t are providedas needed and not always necessary.

One of the source and the drain of the transistor M1 is electricallyconnected to a terminal SL_t, and the other of the source and the drainof the transistor M1 is electrically connected to one of the source andthe drain of the transistor M2.

A gate of the transistor M2 is electrically connected to the terminalRWL_t, and the other of the source and the drain of the transistor M2 iselectrically connected to one of a source and a drain of the transistorM3.

A gate of the transistor M3 is electrically connected to a terminalPRE_t, and the other of the source and the drain of the transistor M3 iselectrically connected to a terminal GND_t.

A second terminal of the capacitor Cs is electrically connected to theterminal CN_t.

An input terminal of the inverter INV is electrically connected to theother of the source and the drain of the transistor M2, and an outputterminal of the inverter INV is electrically connected to a terminalOUT_t.

Note that in FIG. 2, potentials supplied to the terminals are indicatednear the corresponding terminals.

In the circuit MC1, data can be written in the node FN through thetransistor M0, and the written data can be retained by turning off thetransistor M0.

The transistors M1 and M2 have a function of controlling conductionbetween the terminal SL_t and the input terminal of the inverter INV.Specifically, the transistor M1 has a function of controlling theconduction between the terminal SL_t and the input terminal of theinverter INV in accordance with the potential supplied to the node FN.

The transistor M3 has a function of supplying an L level potential tothe input terminal of the inverter INV (supplying an H level potentialto the terminal OUT_t).

The inverter INV has a function of an output buffer.

Hereinafter, a method for measuring the off-state current of thetransistor M0 in the circuit MC1 will be described. Although thetransistors M0 and M3 are n-channel transistors and the transistors M1and M2 are p-channel transistors in the following description, thedescription is also applicable to the case where the transistors M1 andM2 are n-channel transistors.

To measure the off-state current of the transistor M0 of the circuit MC1illustrated in FIG. 2, a current that flows in the terminal WBL_t ismeasured; however, it is difficult to directly measure a minute currentthat flows in the terminal WBL_t when the off-state current of thetransistor M0 is extremely low.

In the case where a wide band gap semiconductor such as an oxidesemiconductor is used for the transistor M0, for example, the off-statecurrent of the transistor M0 is extremely low.

Thus, in the case where the off-state current of the transistor M0 isextremely low, it is preferable to estimate the off-state current of thetransistor M0 from change in the potential of the node FN as describedin Embodiment 1.

<<Operation Example of Circuit MC1>>

FIG. 3 is a timing chart of operation of the circuit MC1. The timingchart in FIG. 3 shows the potentials of, from the top, a terminal VDD_t,the terminal GND_t, the terminal WWL_t, the terminal WBL_t, the terminalBG_t, the terminal RWL_t, the terminal CN_t, the terminal SL_t, theterminal PRE_t, and the terminal OUT_t.

The timing chart in FIG. 3 is divided into a period PW, a period PH, anda period PR. The period PW is a period in which electric charge issupplied to the node FN, the period PH is a period in which the electriccharge supplied to the node FN is retained, and the period PR is aperiod in which the electric charge supplied to the node FN is read.

The period PW is divided into a period PW1, a period PW2, and a periodPW3, and the period PR is divided into a period PR1, a period PR2, and aperiod PR3.

Note that in all the periods, the terminal GND_t, the terminal BG_t, andthe terminal CN_t are supplied with a potential GND. Note that theterminal BG_t may be supplied with a negative potential instead of thepotential GND

In the initial state, the terminal VDD_t is supplied with the potentialV_(DD), the terminal RWL_t is supplied with a potential V_(BL), and theterminal WWL_t, the terminal WBL_t, the terminal SL_t, and the terminalPRE_t are supplied with the potential GND.

Description will be made from the period PW1 in order.

First, the terminal WBL_t is supplied with the potential V_(BL) in theperiod PW1.

Then, the terminal WWL_t is supplied with a potential V_(ON) in theperiod PW2. The potential V_(ON) is preferably higher than the sum ofthe potential V_(BL) and the threshold voltage of the transistor M0. Atthis time, the transistor M0 is turned on and the potential V_(BL) iswritten in the node FN.

Next, in the period PW3, the terminal WWL_t is supplied with a potentialV_(OFF), whereby the transistor M0 is turned off.

After that, in the period PH, the terminal VDD_t, the terminal WBL_t,and the terminal RWL_t are supplied with the potential GND. At thistime, the circuit MC1 is substantially shut off from the power source.

Then, in the period PR1, the terminal VDD_t is supplied with thepotential V_(DD), the terminal RWL_t is supplied with the potentialV_(BL), the terminal SL_t is supplied with a potential V_(SL), and theterminal PRE_t is supplied with the potential V_(DD). The potentialV_(DD) is preferably higher than the threshold voltage of the transistorM3. At this time, the transistor M3 is turned on, the input terminal ofthe inverter INV is supplied with the L level (potential GND), and theterminal OUT outputs the H level (potential V_(DD)).

After that, in the period PR2, the terminal PRE_t is supplied with thepotential GND and the terminal RWL_t is supplied with the potential GND.At this time, the transistor M3 is turned off and the transistor M2 isturned on. Furthermore, a gate-source potential difference (V_(GS)) ofthe transistor M1 is a potential difference between the node FN and theterminal SL_t, that is, a potential difference between the potentialV_(BL) and the potential V_(SL) (V_(GS)=V_(BL)−V_(SL)).

When the potential V_(SL) is sufficiently higher than the potentialV_(BL), V_(GS) of the transistor M1 is lower than the threshold voltageof the transistor M1, so that the transistor M1 is turned on and theterminal OUT_t outputs the L level.

In contrast, when the potential V_(SL) is sufficiently lower than thepotential V_(BL), V_(GS) of the transistor M1 is higher than thethreshold voltage of the transistor M1, so that the transistor M1 isturned off and the terminal OUT_t outputs the H level. In other words,the level of the potential of the terminal OUT_t depends on thepotential V_(SL).

Next, in the period PR3, the terminal RWL_t is supplied with thepotential V_(BL), whereby the transistor M2 is turned off. In addition,the terminal SL_t is supplied with the potential GND.

For example, when the threshold voltage of the transistor M1 and thepotential V_(BL) are −0.5 V and 1.8 V, respectively, and the value ofthe potential V_(SL) is reduced from 2.6 V to 0 V in a step-by-stepmanner, the output of the terminal OUT_t is switched from the L level tothe H level when V_(SL)=2.3 V. By measurement of the point at which theoutput of the terminal OUT_t is switched, the potential of the node FNcan be calculated.

That is, by repeating the cycle from the period PR1 to the period PR3for various values of the potential V_(SL), the potential of the node FNcan be measured.

By repeating the cycle of the period PH and the period PR subsequently,change in the potential of the node FN over time can be measured.

The time-series data of the potential of the node FN obtained by theabove method is fitted to Formula (2) in Embodiment 1, and 3 and T thatare thereby obtained are substituted into Formula (5), whereby theoff-state current of the transistor M0 can be estimated.

The off-state current of the transistor M0 several months to severalyears ahead can be estimated using the above-described measurementmethod. Thus, long-term charge retention characteristics can beestimated.

The circuit MC1 illustrated in FIG. 2 may have a structure in which thetransistor M2 and the terminal RWL_t are not provided as in a circuitMC2 illustrated in FIG. 4.

<<Measurement Environment>>

A measurement sample including a characteristics evaluation circuit maybe put in an inert oven in which temperature is kept constant, asillustrated in FIG. 5. In addition, a constant-temperature air generatormay be used to make the temperature of an atmosphere around measurementequipment constant. The measurement environment is controlled asdescribed above, whereby an adverse effect of noise caused by atemperature change can be reduced.

Specifically, a sample 310 is put in an inert oven 300 and thetemperature of the sample 310 is kept constant. The humidity in theinert oven 300 can be reduced by supplying dry air 320 to the inert oven300 at that time, which provides a low-humidity measurement environment.The sample 310 is connected to a transit portion 331 with a flat cable332. The transit portion is connected to measurement equipment 341 andmeasurement equipment 342 with a coaxial cable 351 and a coaxial cable352, respectively. The measurement equipment 342 sends a signal fortransmitting data of the sample 310 to the transit portion 331. The dataof the sample 310 is supplied from the transit portion 331 to themeasurement equipment 341. Note that a measurement system (including thesample and the measurement equipment) is preferably kept at a constanttemperature. In order to keep the measurement system at a constanttemperature, for example, the measurement system is covered by a heatinsulator 360, a plastic corrugated cardboard, or the like, andconstant-temperature air is supplied using a constant-temperature airgenerator 370 and a duct cable 380. It is preferable that themeasurement system not be entirely covered by the heat insulator 360,the plastic corrugated cardboard, or the like so that a small amount ofconstant-temperature air can flow off to the outside.

Embodiment 3

In this embodiment, more specific structure examples of using thecircuit MC0 and the circuit MC0 a in Embodiment 1 as memory devices aredescribed.

<<Structure Example of Memory Cell>>

FIG. 6 is a circuit diagram of a memory cell that includes thesemiconductor device of one embodiment of the present invention. Amemory cell 10 a in FIG. 6 includes the transistor M0, the transistorM1, the transistor M2, and the capacitor Cs.

The memory cell 10 a is electrically connected to a wiring BL, a wiringSL, a wiring WWL, a wiring RWL, a wiring WCL, and a wiring BG.

The memory cell 10 a includes the circuit MC0 or the circuit MC0 adescribed in Embodiment 1.

A node where one of the source and the drain of the transistor M0, thegate of the transistor M1, and the first terminal of the capacitor Csare electrically connected to one another is referred to as the node FN.One of the source and the drain of the transistor M1 is electricallyconnected to the wiring SL, and the other of the source and the drain ofthe transistor M1 is electrically connected to the wiring BL through thetransistor M2. The gate of the transistor M2 is electrically connectedto the wiring RWL.

The other of the source and the drain of the transistor M0 iselectrically connected to the wiring BL. The first gate of thetransistor M0 is electrically connected to the wiring WWL, and thesecond gate of the transistor M0 is electrically connected to the wiringBG.

The second terminal of the capacitor Cs is electrically connected to thewiring WCL.

The transistor M0 has a function of a switch for controlling writing ofdata in the node FN by being switched between a conducting state and anon-conducting state.

As the transistor M0, it is preferable to use a transistor having a lowcurrent (low off-state current) that flows between a source and a drainin a non-conducting state. Here, the term “low off-state current” meansthat a normalized off-state current per micrometer of channel width witha voltage between a source and a drain set at 1.8 V is 1×10⁻²⁰ A orlower at room temperature, 1×10⁻¹⁸ A or lower at 85° C., or 1×10⁻¹⁶ A orlower at 125° C. An example of a transistor with such a low off-statecurrent is a transistor using a wide band gap semiconductor like anoxide semiconductor transistor.

The node FN can retain 1-bit (binary) data when the transistor M0 isturned off. The node FN can retain not only 1-bit data but also K-bit(2^(K)-valued, K is a natural number of two or more) data.

The case where 1-bit data is retained in the node FN is described below.

Writing and reading by the memory cell 10 a are described below withreference to FIG. 7. Note that the transistor M0 is an n-channeltransistor and the transistors M1 and M2 are p-channel transistors inthe following description.

<<Operation Example of Memory Cell>>

FIG. 7 is a timing chart illustrating an operation example of the memorycell 10 a. The timing chart shows the potentials applied to, from thetop, the wiring WWL, the wiring RWL, the wiring WCL, the wiring BL, thewiring SL, the node FN, and the wiring BG. The timing chart in FIG. 7can be divided into the periods P1 to P5.

The periods P1, P3, and P5 are standby periods of the memory cell 10 a.The period P2 is a write period of the memory cell 10 a. The period P4is a read period of the memory cell 10 a.

Note that in the periods P1 to P5, the wiring WCL is constantly suppliedwith the potential GND. The potential GND is preferably a low powersupply potential or a ground potential.

Furthermore, in the periods P1 to P5, the wiring SL is constantlysupplied with a potential V₃ and the wiring BG is constantly suppliedwith a potential V_(BG). The potential V_(BG) is preferably a negativepotential. When the potential V_(BG) that is a negative potential issupplied, the transistor M0 can be normally off. Here, the term“normally off” means that a current per micrometer of channel widthflowing in the transistor M0 when the wiring WWL is supplied with thepotential GND is 1×10⁻²⁰ A or lower at room temperature, 1×10⁻¹⁸ A orlower at 85° C., or 1×10⁻¹⁶ A or lower at 125° C.

Operations in the respective periods are described in order below.

<Period P1>

First, in the period P1, the wirings WWL BL are supplied with thepotential GND and the wiring RWL is supplied with a potential V₂. Atthis time, the transistor M2 is off and no current flows between thewiring BL and the wiring SL. In order that the transistor M2 can be off,a difference between the potential V₂ and the potential V₃ (V₂−V₃) ispreferably larger than the threshold voltage of the transistor M2.

<Period P2>

Then, in the period P2, the wiring WWL is supplied with a potential V₁and the wiring BL is supplied with the potential V₂ (data “1”) or thepotential GND (data “0”). The potential V₁ is preferably higher than thesum of the potential V₂ and the threshold voltage of the transistor M0.At this time, the transistor M0 is turned on and the data supplied tothe wiring BL is written in the node FN.

<Period P3>

Next, in the period P3, the wiring WWL and the wiring BL are suppliedwith the potential GND. At this time, the transistor M0 is turned offand the data written in the node FN is retained.

<Period P4>

Next, in the period P4, the wiring BL is brought into an electricallyfloating state and the wiring RWL is supplied with the potential GND. Atthis time, the transistor M2 is turned on.

If the data “1” is written in the node FN, the transistor M1 is off, sothat no current flows between the wiring SL and the wiring BL and thewiring BL remains at the potential GND. In order that the transistor M1can be off, a difference between the potential V₂ and the potential V₃(V₂−V₃) is preferably larger than the threshold voltage of thetransistor M1.

If the data “0” is written in the node FN, the transistor M1 is on, sothat the wiring SL and the wiring BL are electrically connected and thewiring BL is charged until it has the potential V₃ (until the potentialof the wiring BL becomes equal to that of the wiring SL). In order thatthe transistor M1 can be on, a difference between the potential GND andthe potential V₃ (−V₃) is preferably smaller than the threshold voltageof the transistor M1. In order that the transistor M2 can be on, adifference between the potential GND and the potential V₃ (−V₃) ispreferably smaller than the threshold voltage of the transistor M2.

In the period P4, the potential of the wiring BL is read to determinethe data written in the node FN.

<Period P5>

Then, in the period P5, the wiring RWL is supplied with the potential V₂and the wiring BL is supplied with the potential GND, so that the datain the node FN is retained.

As described above, through the operations in the periods P1 to P5, datareading from and data writing to the memory cell 10 a can be performed.

<<Structure Example of Memory Device>>

FIG. 8 is a block diagram illustrating a structure example of a memorydevice including the memory cell 10 a.

A memory device 200 in FIG. 8 includes a memory cell array 201 that isprovided with the memory cells 10 a, a row driver 202, and a columndriver 203. The memory cells 10 a in the memory device 200 are arrangedin a matrix of m rows (m is a natural number of two or more) and incolumns (n is a natural number of two or more).

FIG. 8 shows a wiring WWL[m−1] and a wiring RWL[m−1] that are connectedto the memory cells 10 a in the (m−1)-th row, a wiring WWL[m] and awiring RWL[m] that are connected to the memory cells 10 a in the m-throw, the wiring WCL that is connected to the memory cells 10 a in the(m−1)-th and m-th rows, and the wiring BG that is connected to thememory cells 10 a in the (m−1)-th and m-th rows.

In addition, FIG. 8 shows a wiring BL[n−1] that is connected to thememory cells 10 a in the (n−1)-th column, a wiring BL[n] that isconnected to the memory cells 10 a in the n-th column, and the wiring SLthat is connected to the memory cells 10 a in the (n−1)-th and n-thcolumns.

In the memory cell array 201 shown in FIG. 8, the wirings SL, WCL, andBG are shared by adjacent memory cells. This structure reduces the areaoccupied by the wirings. Thus, a memory device with this structure canhave high memory capacity per unit area.

The row driver 202 is a circuit having a function of selectively turningon the transistors M0 and M2 in the memory cells 10 a of each row. Withthe row driver 202, the memory cells 10 a can be selected row by row,and data can be written and read to/from the selected memory cells 10 ain the memory device 200.

The column driver 203 is a circuit having a function of selectivelywriting data in the node FN in the memory cells 10 a of each column, afunction of initializing the potential of the wiring BL, and a functionof making the wiring BL electrically floating. Specifically, the columndriver 203 is a circuit that supplies a potential corresponding to datato the wiring BL. With the column driver 203, the memory cells 10 a canbe selected column by column, and data can be written and read to/fromthe selected memory cells 10 a in the memory device 200.

<<Different Structure Example of Memory Cell>>

Note that in the memory cell 10 a in FIG. 6, the second gate of thetransistor M0 and the wiring BG are not necessarily provided (see amemory cell 10 b in FIG. 9A).

In the memory cell 10 a in FIG. 6, the transistor M2 and the wiring RWLare not necessarily provided (see a memory cell 10 c in FIG. 9B).

In the memory cell 10 a in FIG. 6, the transistors M1 and M2 may ben-channel transistors (see a memory cell 10 d in FIG. 10A).

In the memory cell 10 a in FIG. 6, the wiring BL may be divided into awiring BL1 and a wiring BL2 (see a memory cell 10 e in FIG. 10B).

As described above, the memory device in this embodiment writes andreads data by turning on and off transistors; thus, the number of timesof writing is not limited and high reliability is achieved. In addition,data writing and data reading need only low voltage, leading to lowpower consumption.

Embodiment 4

In this embodiment, structure examples of an oxide semiconductortransistor that can be used for the transistor M0 described inEmbodiments 1 to 3 are shown.

<<Structure Example 1 of Transistor>>

FIGS. 11A to 11D are a top view and cross-sectional views of atransistor 600. FIG. 11A is the top view. FIG. 11B illustrates a crosssection along dashed-dotted line Y1-Y2 in FIG. 11A. FIG. 11C illustratesa cross section along dashed-dotted line X1-X2 in FIG. 11A. FIG. 11iillustrates a cross section along dashed-dotted line X3-X4 in FIG. 11A.In FIGS. 11A to 11D, some components are scaled up or down or omittedfor easy understanding. In some cases, the direction of thedashed-dotted line Y1-Y2 is referred to as a channel length directionand the direction of the dashed-dotted line X1-X2 is referred to as achannel width direction.

Note that the channel length refers to, for example, a distance betweena source (source region or source electrode) and a drain (drain regionor drain electrode) in a region where a semiconductor (or a portionwhere a current flows in a semiconductor when a transistor is on) and agate electrode overlap with each other or a region where a channel isformed in a top view of the transistor. In one transistor, channellengths in all regions are not necessarily the same. In other words, thechannel length of one transistor is not limited to one value in somecases. Therefore, in this specification, the channel length is any oneof values, the maximum value, the minimum value, or the average value ina region where a channel is formed.

The channel width refers to, for example, the length of a portion wherea source and a drain face each other in a region where a semiconductor(or a portion where a current flows in a semiconductor when a transistoris on) and a gate electrode overlap with each other, or a region where achannel is formed. In one transistor, channel widths in all regions arenot necessarily the same. In other words, the channel width of onetransistor is not limited to one value in some cases. Therefore, in thisspecification, the channel width is any one of values, the maximumvalue, the minimum value, or the average value in a region where achannel is formed.

Note that depending on the transistor structure, a channel width in aregion where a channel is actually formed (hereinafter referred to as aneffective channel width) is different from a channel width shown in atop view of a transistor (hereinafter referred to as an apparent channelwidth) in some cases. For example, in a transistor having athree-dimensional structure, an effective channel width is greater thanan apparent channel width shown in a top view of the transistor, and itsinfluence cannot be ignored in some cases. For example, in aminiaturized transistor having a three-dimensional structure, theproportion of a channel region formed in a side surface of asemiconductor is high in some cases. In that case, an effective channelwidth obtained when a channel is actually formed is greater than anapparent channel width shown in the top view.

In a transistor having a three-dimensional structure, an effectivechannel width is difficult to measure in some cases. For example,estimation of an effective channel width from a design value requires anassumption that the shape of a semiconductor is known Therefore, in thecase where the shape of a semiconductor is not known accurately, it isdifficult to measure an effective channel width accurately.

Therefore, in this specification, in a top view of a transistor, anapparent channel width that is a length of a portion where a source anda drain face each other in a region where a semiconductor and a gateelectrode overlap with each other is referred to as a surrounded channelwidth (SCW) in some cases. Furthermore, in this specification, in thecase where the term “channel width” is simply used, it may denote asurrounded channel width and an apparent channel width. Alternatively,in this specification, in the case where the term “channel width” issimply used, it may denote an effective channel width in some cases.Note that the values of a channel length, a channel width, an effectivechannel width, an apparent channel width, a surrounded channel width,and the like can be determined by obtaining and analyzing across-sectional TEM image and the like.

Note that in the case where field-effect mobility, a current value perchannel width, and the like of a transistor are obtained by calculation,a surrounded channel width may be used for the calculation. In thatcase, the values may be different from those calculated using aneffective channel width in some cases.

The transistor 600 includes a substrate 640; an insulating film 650 overthe substrate 640; a conductive film 674 over the insulating film 650;an insulating film 651 covering the conductive film 674; an insulatingfilm 656 over the insulating film 651; an insulating film 652 over theinsulating film 656; a semiconductor 661 and a semiconductor 662 stackedover the insulating film 652 in this order; a conductive film 671 and aconductive film 672 in contact with the top surface of the semiconductor662; a semiconductor 663 in contact with the semiconductor 661, thesemiconductor 662, the conductive film 671, and the conductive film 672;an insulating film 653 and a conductive film 673 over the semiconductor663; an insulating film 654 over the conductive film 673 and theinsulating film 653; and an insulating film 655 over the insulating film654. Note that the semiconductor 661, the semiconductor 662, and thesemiconductor 663 are collectively referred to as a semiconductor 660.

The conductive film 671 functions as one of a source electrode and adrain electrode of the transistor 600. The conductive film 672 functionsas the other of the source electrode and the drain electrode of thetransistor 600.

The conductive film 673 functions as a first gate electrode of thetransistor 600.

The insulating film 653 functions as a first gate insulating film of thetransistor 600.

The conductive film 674 has a function as a second gate electrode of thetransistor 600.

Potentials applied to the conductive films 673 and 674 may be the sameor different from each other. Note that the conductive film 674 isunnecessary in some cases.

The insulating films 650, 651, 652, and 656 function as base insulatingfilms. The insulating films 651, 652 and 656 also function as a secondgate insulating film of the transistor 600.

The insulating films 654 and 655 each function as a protectiveinsulating film or an interlayer insulating film.

As illustrated in FIG. 11C, a side surface of the semiconductor 662 issurrounded by the conductive film 673. With such a structure, thesemiconductor 662 can be electrically surrounded by an electric field ofthe conductive film 673 (a transistor structure in which a semiconductoris electrically surrounded by an electric field of a conductive film(gate electrode) is referred to as a surrounded channel (s-channel)structure). Therefore, a channel is formed in the entire semiconductor662 (bulk) in some cases. In the s-channel structure, a large amount ofcurrent can flow between a source and a drain of a transistor, so that ahigh current in an on state (on-state current) can be achieved. Thes-channel structure enables a transistor to operate at high frequency.

The s-channel structure, because of its high on-state current, issuitable for a semiconductor device such as large-scale integration(LSI) which requires a miniaturized transistor. A semiconductor deviceincluding the miniaturized transistor can have a high integration degreeand high density. The transistor preferably has, for example, a regionwhere a channel length is greater than or equal to 10 nm and less than 1μm, more preferably greater than or equal to 10 nm and less than 100 nm,still more preferably greater than or equal to 10 nm and less than 70nm, yet still more preferably greater than or equal to 10 nm and lessthan 60 nm, and yet still more preferably greater than or equal to 10 nmand less than 30 nm. In addition, the transistor preferably has, forexample, a region where a channel width is greater than or equal to 10nm and less than 1 μm, more preferably greater than or equal to 10 nmand less than 100 nm, still more preferably greater than or equal to 10nm and less than 70 nm, yet still more preferably greater than or equalto 10 nm and less than 60 nm, and yet still more preferably greater thanor equal to 10 nm and less than 30 nm.

Since a high on-state current can be obtained, the s-channel structureis suitable for a transistor that needs to operate at high frequency. Asemiconductor device including the transistor can operate at highfrequency.

Components of the transistor 600 are described below.

<Semiconductor>

First, semiconductors which can be used as the semiconductors 661 to 663will be described.

In the transistor 600, it is preferable that the current flowing betweena source and drain in an off state (off-state current) be low. Anexample of a transistor with a low off-state current is a transistorincluding an oxide semiconductor as a semiconductor

The semiconductor 662 is, for example, an oxide semiconductor containingindium (In). The semiconductor 662 has a high carrier mobility (electronmobility) when containing, for example, indium. The semiconductor 662preferably contains an element M. The element M is preferably aluminum(Al), gallium (Ga), yttrium (Y), tin (Sn), or the like. Other elementswhich can be used as the element M include boron (B), silicon (Si),titanium (Ti), iron (Fe), nickel (Ni), germanium (Ge), zirconium (Zr),molybdenum (Mo), lanthanum (La), cerium (Ce), neodymium (Nd), hafnium(Hf), tantalum (Ta), and tungsten (W). Note that two or more of theabove elements may be used in combination as the element M. The elementM is an element having high bonding energy with oxygen, for example. Theelement M is an element whose bonding energy with oxygen is higher thanthat of indium. The element M is an element that can increase the energygap of the oxide semiconductor, for example. Furthermore, thesemiconductor 662 preferably contains zinc (Zn). When the oxidesemiconductor contains zinc, the oxide semiconductor is easilycrystallized in some cases.

Note that the semiconductor 662 is not limited to the oxidesemiconductor containing indium. The semiconductor 662 may be, forexample, an oxide semiconductor which does not contain indium andcontains zinc, an oxide semiconductor which does not contain indium andcontains gallium, or an oxide semiconductor which does not containindium and contains tin, e.g., a zinc tin oxide or a gallium tin oxide.

For the semiconductor 662, an oxide with a wide energy gap may be used.For example, the energy gap of the semiconductor 662 is greater than orequal to 2.5 eV and less than or equal to 4.2 eV, preferably greaterthan or equal to 2.8 eV and less than or equal to 3.8 eV, morepreferably greater than or equal to 3 eV and less than or equal 5 to 3.5eV.

The semiconductor 662 is preferably a CAAC-OS film which will bedescribed later.

For example, the semiconductor 661 and the semiconductor 663 include oneor more, or two or more elements other than oxygen included in thesemiconductor 662. Since the semiconductor 661 and the semiconductor 663each include one or more, or two or more elements other than oxygenincluded in the semiconductor 662, an interface state is less likely tobe formed at the interface between the semiconductor 661 and thesemiconductor 662 and the interface between the semiconductor 662 andthe semiconductor 663.

In the case of using an In-M-Zn oxide as the semiconductor 661 and thesummation of In and M is assumed to be 100 atomic %, the proportions ofIn and M are preferably set to be less than 50 atomic % and greater than50 atomic %, respectively, more preferably less than 25 atomic % andgreater than 75 atomic %, respectively. In the case where thesemiconductor 661 is formed by a sputtering method, a sputtering targetwith the above composition, for example, a sputtering target containingIn, M, and Zn at an atomic ratio of 1:3:2, is preferably used.

In the case where an In-M-Zn oxide is used for the semiconductor 662 andthe summation of In and M is assumed to be 100 atomic %, the proportionsof In and M are preferably set to be greater than 25 atomic % and lessthan 75 atomic %, respectively, and more preferably greater than 34atomic % and less than 66 atomic %, respectively. In the case where thesemiconductor 662 is formed by a sputtering method, a sputtering targetwith the above composition, for example, a sputtering target containingIn, M, and Zn at an atomic ratio of 1:1:1, 1:1:1.2, 2:1:3, 3:1:2, or4:2:4.1, is preferably used. In particular, when a sputtering targetcontaining In, Ga, and Zn at an atomic ratio of 4:2:4.1 is used, thesemiconductor 662 may contain In, Ga, and Zn at an atomic ratio ofaround 4:2:3.

In the case of using an In-M-Zn oxide as the semiconductor 663, when thesummation of In and M is assumed to be 100 atomic %, the proportions ofIn and M are preferably set to be less than 50 atomic % and greater than50 atomic %, respectively, more preferably less than 25 atomic % andgreater than 75 atomic %, respectively. Note that the semiconductor 663and the semiconductor 661 may be formed using the same type of oxide.Note that the semiconductor 661 and/or the semiconductor 663 do/does notnecessarily contain indium in some cases. For example, the semiconductor661 and/or the semiconductor 663 may be gallium oxide.

Next, a function and an effect of the semiconductor 660 in which thesemiconductors 661 to 663 are stacked will be described using an energyband diagram in FIG. 12B. FIG. 12A is an enlarged view of the channelportion of the transistor 600 illustrated in FIG. 11B. FIG. 12B shows anenergy band structure of a portion along the chain line A1-A2 in FIG.12A. FIG. 12B illustrates the energy band structure of a channelformation region of the transistor 600.

In FIG. 12B, EcI1, EcS1, EcS2, EcS3, and EcI2 indicate the energy of theconduction band minimum of the insulating film 652, the semiconductor661, the semiconductor 662, the semiconductor 663, and the insulatingfilm 653, respectively.

Here, a difference in energy between the vacuum level and the conductionband minimum (the difference is also referred to as electron affinity)corresponds to a value obtained by subtracting an energy gap from adifference in energy between the vacuum level and the valence bandmaximum (the difference is also referred to as ionization potential).The energy gap can be measured using a spectroscopic ellipsometer. Theenergy difference between the vacuum level and the valence band maximumcan be measured using an ultraviolet photoelectron spectroscopy (UPS)device.

Since the insulating film 652 and the insulating film 653 areinsulators, EcI2 and EcI1 are closer to the vacuum level than EcS1,EcS2, and EcS3 are (i.e., the insulating film 652 and the insulatingfilm 653 have a smaller electron affinity than the semiconductor 661,the semiconductor 662, and the semiconductor 663).

As the semiconductor 662, an oxide having an electron affinity higherthan those of the semiconductors 661 and 663 is used. For example, asthe semiconductor 662, an oxide having an electron affinity higher thanthose of the semiconductors 661 and 663 by 0.07 eV or higher and 1.3 eVor lower, preferably 0.1 eV or higher and 0.7 eV or lower, morepreferably 0.15 eV or higher and 0.4 eV or lower is used. Note that theelectron affinity refers to an energy difference between the vacuumlevel and the conduction band minimum.

An indium gallium oxide has a small electron affinity and a highoxygen-blocking property. Therefore, the semiconductor 663 preferablyincludes an indium gallium oxide. The gallium atomic ratio [Ga/(In+Ga)]is, for example, higher than or equal to 70%, preferably higher than orequal to 80%, more preferably higher than or equal to 90%.

At this time, when a gate voltage is applied, a channel is formed in thesemiconductor 662 having the highest electron affinity among thesemiconductors 661 to 663.

Here, in some cases, there is a mixed region of the semiconductor 661and the semiconductor 662 between the semiconductor 661 and thesemiconductor 662. Furthermore, in some cases, there is a mixed regionof the semiconductor 662 and the semiconductor 663 between thesemiconductor 662 and the semiconductor 663. The mixed region has a lowinterface state density. For that reason, the stack of the semiconductor661, the semiconductor 662, and the semiconductor 663 has a bandstructure where energy at each interface and in the vicinity of theinterface is changed continuously (continuous junction).

At this time, electrons move mainly in the semiconductor 662, not in thesemiconductor 661 and the semiconductor 663. As described above, whenthe interface state density at the interface between the semiconductor661 and the semiconductor 662 and the interface state density at theinterface between the semiconductor 662 and the semiconductor 663 aredecreased, electron movement in the semiconductor 662 is less likely tobe inhibited and the on-sate current of the transistor can be increased.

As factors of inhibiting electron movement are decreased, the on-statecurrent of the transistor can be increased. For example, in the casewhere there is no factor of inhibiting electron movement, electrons areassumed to be efficiently moved. Electron movement is inhibited, forexample, in the case where physical unevenness in a channel formationregion is large.

To increase the on-state current of the transistor, for example, rootmean square (RMS) roughness with a measurement area of 1 μm×1 μm of thetop surface or the bottom surface of the semiconductor 662 (a formationsurface; here, the top surface of the semiconductor 661) is less than 1nm, preferably less than 0.6 nm, more preferably less than 0.5 nm, stillmore preferably less than 0.4 nm. The average surface roughness (alsoreferred to as Ra) with the measurement area of 1 μm×1 μm is less than 1nm, preferably less than 0.6 nm, more preferably less than 0.5 nm, stillmore preferably less than 0.4 nm. The maximum difference (P−V) with themeasurement area of 1 μm×1 μm is less than 10 nm, preferably less than 9nm, more preferably less than 8 nm, still more preferably less than 7nm. RMS roughness, Ra, and P−V can be measured using, for example, ascanning probe microscope SPA-500 manufactured by SII Nano TechnologyInc.

The electron movement is also inhibited, for example, in the case wherethe density of defect states is high in a region where a channel isformed.

For example, in the case where the semiconductor 662 contains oxygenvacancies (also denoted by V_(O)), donor levels are formed by entry ofhydrogen into sites of oxygen vacancies in some cases. A state in whichhydrogen enters sites of oxygen vacancies is denoted by V_(O)H in thefollowing description in some cases. V_(O)H is a factor of decreasingthe on-state current of the transistor because V_(O)H scatterselectrons. Note that sites of oxygen vacancies become more stable byentry of oxygen than by entry of hydrogen. Thus, by decreasing oxygenvacancies in the semiconductor 662, the on-state current of thetransistor can be increased in some cases.

For example, the hydrogen concentration at a certain depth in thesemiconductor 662 or in a certain region of the semiconductor 662, whichis measured by secondary ion mass spectrometry (SIMS), is higher than orequal to 1×10¹⁶ atoms/cm³ and lower than or equal to 2×10²⁰ atoms/cm³,preferably higher than or equal to 1×10¹⁶ atoms/cm³ and lower than orequal to 5×10¹⁹ atoms/cm³, more preferably higher than or equal to1×10¹⁶ atoms/cm³ and lower than or equal to 1×10¹⁹ atoms/cm³, still morepreferably higher than or equal to 1×10¹⁶ atoms/cm³ and lower than orequal to 5×10¹⁸ atoms/cm³.

To decrease oxygen vacancies in the semiconductor 662, for example,there is a method in which excess oxygen in the insulating film 652 ismoved to the semiconductor 662 through the semiconductor 661. In thiscase, the semiconductor 661 is preferably a layer having anoxygen-transmitting property (a layer through which oxygen passes or istransmitted).

In the case where the transistor has an s-channel structure, a channelis formed in the whole of the semiconductor 662. Therefore, as thesemiconductor 662 has a larger thickness, a channel region becomeslarger. In other words, the thicker the semiconductor 662 is, the largerthe on-state current of the transistor is.

Moreover, the thickness of the semiconductor 663 is preferably as smallas possible to increase the on-state current of the transistor. Forexample, the semiconductor 663 has a region with a thickness of lessthan 10 nm, preferably less than or equal to 5 nm, more preferably lessthan or equal to 3 nm. Meanwhile, the semiconductor 663 has a functionof blocking entry of elements other than oxygen (such as hydrogen andsilicon) included in the adjacent insulator into the semiconductor 662where a channel is formed. For this reason, it is preferable that thesemiconductor 663 have a certain thickness. For example, thesemiconductor 663 may have a region with a thickness of greater than orequal to 0.3 nm, preferably greater than or equal to 1 nm, morepreferably greater than or equal to 2 nm. The semiconductor 663preferably has an oxygen blocking property to suppress outward diffusionof oxygen released from the insulating film 652 and the like.

To improve reliability, preferably, the thickness of the semiconductor661 is large and the thickness of the semiconductor 663 is small. Forexample, the semiconductor 661 has a region with a thickness of greaterthan or equal to 10 nm, preferably greater than or equal to 20 nm, morepreferably greater than or equal to 40 nm, still more preferably greaterthan or equal to 60 nm. When the thickness of the semiconductor 661 ismade large, the distance from an interface between the adjacentinsulator and the semiconductor 661 to the semiconductor 662 in which achannel is formed can be large. However, to prevent the productivity ofthe semiconductor device from being decreased, the semiconductor 661 hasa region with a thickness of, for example, less than or equal to 200 nm,preferably less than or equal to 120 nm, more preferably less than orequal to 80 nm.

For example, a region with a silicon concentration measured by SIMSanalysis of higher than or equal to 1×10¹⁶ atoms/cm³ and lower than1×10¹⁹ atoms/cm³, preferably higher than or equal to 1×10¹⁶ atoms/cm³and lower than 5×10¹⁸ atoms/cm³, more preferably higher than or equal to1×10¹⁶ atoms/cm³ and lower than 2×10¹⁸ atoms/cm³ is provided between thesemiconductor 662 and the semiconductor 661. A region with a siliconconcentration measured by SIMS of higher than or equal to 1×10¹⁶atoms/cm³ and lower than 1×10¹⁹ atoms/cm³, preferably higher than orequal to 1<10¹⁶ atoms/cm³ and lower than 5×10¹⁸ atoms/cm³, morepreferably higher than or equal to 1×10¹⁶ atoms/cm³ and lower than2×10¹⁸ atoms/cm³ is provided between the semiconductor 662 and thesemiconductor 663.

It is preferable to reduce the concentration of hydrogen in thesemiconductor 661 and the semiconductor 663 in order to reduce theconcentration of hydrogen in the semiconductor 662. The semiconductor661 and the semiconductor 663 each have a region in which theconcentration of hydrogen measured by SIMS is higher than or equal to1×10¹⁶ atoms/cm³ and lower than or equal to 2×10²⁰ atoms/cm³, preferablyhigher than or equal to 1×10¹⁶ atoms/cm³ and lower than or equal to5×10¹⁹ atoms/cm³, more preferably higher than or equal to 1×10¹⁶atoms/cm³ and lower than or equal to 1×10¹⁹ atoms/cm³, still morepreferably higher than or equal to 1×10¹⁶ atoms/cm³ and lower than orequal to 5×10¹⁸ atoms/cm³. It is preferable to reduce the concentrationof nitrogen in the semiconductor 661 and the semiconductor 663 in orderto reduce the concentration of nitrogen in the semiconductor 662. Thesemiconductor 661 and the semiconductor 663 each have a region in whichthe concentration of nitrogen measured by SIMS is higher than or equalto 1×10¹⁶ atoms/cm³ and lower than 5×10¹⁹ atoms/cm³, preferably higherthan or equal to 1×10¹⁶ atoms/cm³ and lower than or equal to 5×10¹⁸atoms/cm³, more preferably higher than or equal to 1×10¹⁶ atoms/cm³ andlower than or equal to 1×10¹⁸ atoms/cm³, still more preferably higherthan or equal to 1×10¹⁶ atoms/cm³ and lower than or equal to 5×10¹⁷atoms/cm³.

The above three-layer structure is an example. For example, a two-layerstructure without the semiconductor 661 or the semiconductor 663 may beemployed. A four-layer structure in which any one of the semiconductorsshown as examples of the semiconductor 661, the semiconductor 662, andthe semiconductor 663 is provided under or over the semiconductor 661 orunder or over the semiconductor 663 may be employed. An n-layerstructure (n is an integer of 5 or more) may be employed in which anyone of the semiconductors shown as examples of the semiconductor 661,the semiconductor 662, and the semiconductor 663 is provided at two ormore of the following positions: over the semiconductor 661, under thesemiconductor 661, over the semiconductor 663, and under thesemiconductor 663.

<Substrate>

As the substrate 640, for example, an insulator substrate, asemiconductor substrate, or a conductor substrate may be used. As theinsulator substrate, for example, a glass substrate, a quartz substrate,a sapphire substrate, a stabilized zirconia substrate (e.g., anyttria-stabilized zirconia substrate), or a resin substrate is used. Asthe semiconductor substrate, for example, a single materialsemiconductor substrate made of silicon, germanium, or the like, acompound semiconductor substrate made of silicon carbide, silicongermanium, gallium arsenide, indium phosphide, zinc oxide, or galliumoxide, or the like is used. The above semiconductor substrate in whichan insulator region is provided, e.g., a silicon on insulator (SOI)substrate may also be used. As the conductor substrate, a graphitesubstrate, a metal substrate, an alloy substrate, a conductive resinsubstrate, or the like is used. A substrate including a metal nitride, asubstrate including a metal oxide, or the like is used. An insulatorsubstrate provided with a conductor or a semiconductor, a semiconductorsubstrate provided with a conductor or an insulator, a conductorsubstrate provided with a semiconductor or an insulator, or the like mayalso be used. Alternatively, any of these substrates over which anelement is provided may be used. As the element provided over thesubstrate, a capacitor, a resistor, a switching element, alight-emitting element, a memory element, or the like is used.

Alternatively, a flexible substrate may be used as the substrate 640. Asa method for providing a transistor over a flexible substrate, there isa method in which the transistor is formed over a non-flexible substrateand then the transistor is separated and transferred to the substrate640 which is a flexible substrate. In that case, a separation layer ispreferably provided between the non-flexible substrate and thetransistor. As the substrate 640, a sheet, a film, or a foil containinga fiber may be used. The substrate 640 may have elasticity. Thesubstrate 640 may have a property of returning to its original shapewhen bending or pulling is stopped. Alternatively, the substrate 640 mayhave a property of not returning to its original shape. The thickness ofthe substrate 640 is, for example, greater than or equal to 5 μm andless than or equal to 700 μm, preferably greater than or equal to 10 μmand less than or equal to 500 μm, more preferably greater than or equalto 15 μm and less than or equal to 300 μm. When the substrate 640 has asmall thickness, the weight of the semiconductor device can be reduced.When the substrate 640 has a small thickness, even in the case of usingglass or the like, the substrate 640 may have elasticity or a propertyof returning to its original shape when bending or pulling is stopped.Therefore, an impact applied to the semiconductor device over thesubstrate 640, which is caused by dropping or the like, can be reduced.That is, a durable semiconductor device can be provided.

For the substrate 640 which is a flexible substrate, for example, metal,an alloy, resin, glass, or fiber thereof can be used. The flexiblesubstrate 640 preferably has a lower coefficient of linear expansionbecause deformation due to an environment is suppressed. The flexiblesubstrate 640 is formed using, for example, a material whose coefficientof linear expansion is lower than or equal to 1×10⁻³/K, lower than orequal to 5×10⁻⁵/K, or lower than or equal to 1×10⁻⁵/K. Examples of theresin include polyester, polyolefin, polyamide (e.g., nylon or aramid),polyimide, polycarbonate, acrylic, and polytetrafluoroethylene (PTFE).In particular, aramid is preferably used for the flexible substrate 640because of its low coefficient of linear expansion

<Base Insulating Film>

The insulating film 650 has a function of electrically isolating thesubstrate 640 and the conductive film 674 from each other.

The insulating film 650 or 651 is formed using an insulating film havinga single-layer structure or a stacked-layer structure. Examples of thematerial of the insulating film include aluminum oxide, magnesium oxide,silicon oxide, silicon oxynitride, silicon nitride oxide, siliconnitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide,lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide.

The insulating film 651 may be formed using silicon oxide with high stepcoverage which is formed by reacting tetraethyl orthosilicate (TEOS),silane, or the like with oxygen, nitrous oxide, or the like.

After the insulating film 651 is formed, the insulating film 651 may besubjected to planarization treatment using a CMP method or the like toimprove the planarity of the top surface thereof.

The insulating film 652 preferably includes an oxide. In particular, theinsulating film 652 preferably includes an oxide material from whichpart of oxygen is released by heating. The insulating film 652preferably includes an oxide containing oxygen in excess of that in thestoichiometric composition. Part of oxygen is released by heating fromthe oxide film containing oxygen in excess of that in the stoichiometriccomposition. Oxygen released from the insulating film 651 or 652 issupplied to the semiconductor 660 that is an oxide semiconductor, sothat oxygen vacancies in the oxide semiconductor can be reduced.Consequently, changes in the electrical characteristics of thetransistor can be reduced and the reliability of the transistor can beimproved.

The oxide film containing oxygen in excess of that in the stoichiometriccomposition is an oxide film in which the amount of released oxygenconverted into oxygen atoms is greater than or equal to 1.0×10¹⁸atoms/cm³, preferably greater than or equal to 3.0×10²⁰ atoms/cm³ inthermal desorption spectroscopy (TDS) analysis, for example. Note thatthe temperature of the film surface in the TDS analysis is preferablyhigher than or equal to 100° C. and lower than or equal to 700° C., orhigher than or equal to 100° C. and lower than or equal to 500° C.

The insulating film 652 preferably contains an oxide that can supplyoxygen to the semiconductor 660. For example, a material containingsilicon oxide or silicon oxynitride is preferably used.

Alternatively, a metal oxide such as aluminum oxide, aluminumoxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttriumoxynitride, hafnium oxide, or hafnium oxynitride may be used for theinsulating film 652.

To make the insulating film 652 contain excess oxygen, the insulatingfilm 652 is formed in an oxygen atmosphere, for example. Alternatively,a region containing excess oxygen may be formed by introducing oxygeninto the insulating film 652 that has been formed Both the methods maybe combined.

For example, oxygen (at least including any of oxygen radicals, oxygenatoms, and oxygen ions) may be introduced into the insulating film 652that has been formed, so that a region containing excess oxygen isformed. Oxygen can be introduced by, for example, an ion implantationmethod, an ion doping method, a plasma immersion ion implantationmethod, plasma treatment, or the like.

A gas containing oxygen can be used for oxygen introducing treatment. Asthe gas containing oxygen, oxygen, nitrous oxide, nitrogen dioxide,carbon dioxide, carbon monoxide, or the like can be used. Furthermore, arare gas may be included in the gas containing oxygen for the oxygenintroducing treatment. Moreover, hydrogen or the like may be included.For example, a mixed gas of carbon dioxide, hydrogen, and argon may beused.

After the insulating film 652 is formed, the insulating film 652 may besubjected to planarization treatment using a CMP method or the like toimprove the planarity of the top surface thereof.

The insulating film 656 has a passivation function of preventing oxygencontained in the insulating film 652 from decreasing by bonding to metalcontained in the conductive film 674.

The insulating film 656 has a function of blocking oxygen, hydrogen,water, alkali metal, alkaline earth metal, and the like. Providing theinsulating film 656 can prevent outward diffusion of oxygen from thesemiconductor 660 and entry of hydrogen, water, or the like into thesemiconductor 660 from the outside.

The insulating film 656 can be, for example, a nitride insulating film.The nitride insulating film is formed using silicon nitride, siliconnitride oxide, aluminum nitride, aluminum nitride oxide, or the like.Note that instead of the nitride insulating film, an oxide insulatingfilm having a blocking effect against oxygen, hydrogen, water, and thelike may be provided. As examples of the oxide insulating film, analuminum oxide film, an aluminum oxynitride film, a gallium oxide film,a gallium oxynitride film, an yttrium oxide film, an yttrium oxynitridefilm, a hafnium oxide film, a hafnium oxynitride film, and the like canbe given.

In the transistor 600, the threshold voltage can be controlled byinjecting electrons into a charge trap layer. The charge trap layer ispreferably provided in the insulating film 651 or the insulating film656. For example, when the insulating film 656 is formed using hafniumoxide, aluminum oxide, tantalum oxide, aluminum silicate, or the like,the insulating film 656 can function as a charge trap layer.

<Gate Electrode, Source Electrode, and Drain Electrode>

The conductive films 671 to 673 each preferably have a single-layerstructure or a layered structure of a conductive film containing alow-resistance material selected from copper (Cu), tungsten (W),molybdenum (Mo), gold (Au), aluminum (Al), manganese (Mn), titanium(Ti), tantalum (Ta), nickel (Ni), chromium (Cr), lead (Pb), tin (Sn),iron (Fe), cobalt (Co), ruthenium (Ru), platinum (Pt), iridium (Ir), andstrontium (Sr), an alloy of such a low-resistance material, or acompound containing such a material as its main component. It isparticularly preferable to use a high-melting-point material which hasboth heat resistance and conductivity, such as tungsten or molybdenum.In addition, the conductive film is preferably formed using alow-resistance conductive material such as aluminum or copper. Theconductive film is more preferably formed using a Cu—Mn alloy, in whichcase manganese oxide formed at the interface with an insulatorcontaining oxygen has a function of preventing Cu diffusion.

The conductive films 671 to 673 are preferably formed using a conductiveoxide including noble metal, such as iridium oxide, ruthenium oxide, orstrontium ruthenate. Such a conductive oxide hardly takes oxygen from anoxide semiconductor even when it is in contact with the oxidesemiconductor and hardly generates oxygen vacancies in the oxidesemiconductor.

<Gate Insulating Film>

The insulating film 653 can be formed using an insulating filmcontaining at least one of aluminum oxide, magnesium oxide, siliconoxide, silicon oxynitride, silicon nitride oxide, silicon nitride,gallium oxide, germanium oxide, yttrium oxide, zirconium oxide,lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Theinsulating film 653 may be a stack including any of the above materials.The insulating film 653 may contain lanthanum (La), nitrogen, orzirconium (Zr) as an impurity.

An example of a layered structure of the insulating film 653 isdescribed. The insulating film 653 contains oxygen, nitrogen, silicon,or hafnium, for example. Specifically, the insulating film 653preferably includes hafnium oxide and silicon oxide or siliconoxynitride.

Hafnium oxide has a higher dielectric constant than silicon oxide andsilicon oxynitride. Therefore, the thickness of the insulating film 653can be larger when hafnium oxide is used than when silicon oxide isused; as a result, a leakage current due to a tunnel current can be low.That is, it is possible to provide a transistor with a low off-statecurrent.

<Protective Insulating Film>

The insulating film 654 has a blocking effect against oxygen, hydrogen,water, alkali metal, alkaline earth metal, and the like. Providing theinsulating film 654 can prevent outward diffusion of oxygen from thesemiconductor 660 and entry of hydrogen, water, or the like into thesemiconductor 660 from the outside.

The insulating film 654 can be, for example, a nitride insulating film.The nitride insulating film is formed using silicon nitride, siliconnitride oxide, aluminum nitride, aluminum nitride oxide, or the like.Note that instead of the nitride insulating film, an oxide insulatingfilm having a blocking effect against oxygen, hydrogen, water, and thelike, may be provided. As the oxide insulating film, an aluminum oxidefilm, an aluminum oxynitride film, a gallium oxide film, a galliumoxynitride film, an yttrium oxide film, an yttrium oxynitride film, ahafnium oxide film, and a hafnium oxynitride film can be given.

An aluminum oxide film is preferably used as the insulating film 654because it is highly effective in preventing transmission of both oxygenand impurities such as hydrogen and moisture.

After the insulating film 654 is formed, heat treatment is preferablyperformed. Through this heat treatment, oxygen can be supplied to thesemiconductor 660 from the insulating film 652 or the like; thus, oxygenvacancies in the semiconductor 660 can be reduced.

The insulating film 655 can be formed using an insulator containing atleast one of aluminum oxide, aluminum nitride oxide, magnesium oxide,silicon oxide, silicon oxynitride, silicon nitride oxide, siliconnitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide,lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and thelike. Alternatively, for the insulating film 655, an organic resin suchas a polyimide resin, a polyamide resin, an acrylic resin, a siloxaneresin, an epoxy resin, or a phenol resin can be used. The insulatingfilm 655 may be a stack including any of the above materials.

<Structure Example 2 of Transistor>

In the transistor 600 in FIGS. 11A to 11D, the conductive film 674 isnot necessarily provided. FIGS. 13A to 13D show an example of such acase. FIGS. 13A to 13D are a top view and cross-sectional views of atransistor 600 a. FIG. 13A is the top view. FIG. 13B illustrates a crosssection along dashed-dotted line Y1-Y2 in FIG. 13A. FIG. 13C illustratesa cross section along dashed-dotted line X1-X2 in FIG. 13A. FIG. 13Dillustrates a cross section along dashed-dotted line X3-X4 in FIG. 13A.In FIGS. 13A to 13D, some components are scaled up or down or omittedfor easy understanding. In some cases, the direction of thedashed-dotted line Y1-Y2 is referred to as a channel length directionand the direction of the dashed-dotted line X1-X2 is referred to as achannel width direction.

The transistor 600 a shown in FIGS. 13A to 13D is the transistor 600shown in FIGS. 11A to 11D that is not provided with the conductive film674 and the insulating film 650.

<Structure Example 3 of Transistor>

In the transistor 600 in FIGS. 11A to 11D, the conductive film 673 andthe conductive film 674 may be connected to each other. FIGS. 14A to 14Dshow an example of such a case.

FIGS. 14A to 14D are a top view and cross-sectional views of atransistor 600 b. FIG. 14A is the top view. FIG. 14B illustrates a crosssection along dashed-dotted line Y1-Y2 in FIG. 14A. FIG. 14C illustratesa cross section along dashed-dotted line X1-X2 in FIG. 14A. FIG. 14Dillustrates a cross section along dashed-dotted line X3-X4 in FIG. 14A.In FIGS. 14A to 14D, some components are scaled up or down or omittedfor easy understanding. In some cases, the direction of thedashed-dotted line Y1-Y2 is referred to as a channel length directionand the direction of the dashed-dotted line X1-X2 is referred to as achannel width direction.

In the transistor 600 b, an opening portion 675 is provided in theinsulating film 653, the semiconductor 663, the insulating film 652, andthe insulating film 656, and the conductive film 673 and the conductivefilm 674 are connected to each other through the opening portion 675.

<Structure Example 4 of Transistor>

In the transistor 600 illustrated in FIGS. 11A to 11D, the semiconductor663 and the insulating film 653 may be etched at the same time when theconductive film 673 is formed by etching. FIG. 15 shows an example ofsuch a case.

FIG. 15 illustrates a transistor 600 c in which the semiconductor 663and the insulating film 653 in FIG. 11B are provided only under theconductive film 673.

<Structure Example 5 of Transistor>

In the transistor 600 illustrated in FIGS. 11A to 11D, the conductivefilms 671 and 672 may be in contact with side surfaces of thesemiconductors 661 and 662. FIG. 16 shows an example of such a case.

FIG. 16 illustrates a transistor 600 d in which the conductive films 671and 672 in FIG. 11B are in contact with the side surfaces of thesemiconductors 661 and 662.

<Structure Example 6 of Transistor>

In the transistor 600 illustrated in FIGS. 11A to 11D, the conductivefilm 671 may be a stack including a conductive film 671 a and aconductive film 671 b. Furthermore, the conductive film 672 may be astack including a conductive film 672 a and a conductive film 672 b.FIG. 17 illustrates an example of such a case.

FIG. 17 illustrates a transistor 600 e in which the conductive film 671and the conductive film 672 in FIG. 11B are a stack including theconductive films 671 a and 671 b and a stack including the conductivefilms 672 a and 672 b, respectively.

The conductive films 671 b and 672 b may be formed using a transparentconductor, an oxide semiconductor, a nitride semiconductor, or anoxynitride semiconductor, for example. The conductive films 671 b and672 b may be formed using, for example, a film containing indium, tin,and oxygen, a film containing indium and zinc, a film containing indium,tungsten, and zinc, a film containing tin and zinc, a film containingzinc and gallium, a film containing zinc and aluminum, a film containingzinc and fluorine, a film containing zinc and boron, a film containingtin and antimony, a film containing tin and fluorine, a film containingtitanium and niobium, or the like. Alternatively, any of these films maycontain hydrogen, carbon, nitrogen, silicon, germanium, or argon.

The conductive films 671 b and 672 b may have a property of transmittingvisible light. Alternatively, the conductive films 671 b and 672 b mayhave a property of not transmitting visible light, ultraviolet light,infrared light, or X-rays by reflecting or absorbing it. In some cases,such a property can suppress change in electrical characteristics of thetransistor due to stray light.

The conductive films 671 b and 672 b may preferably be formed using alayer which does not form a Schottky barrier with the semiconductor 662or the like. Accordingly, on-state characteristics of the transistor canbe improved.

Each of the conductive films 671 a and 672 a may be formed to have, forexample, a single-layer structure or a layered structure including aconductor containing one or more kinds of boron, nitrogen, oxygen,fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese,cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum,ruthenium, silver, indium, tin, tantalum, and tungsten. For example, analloy film or a compound film may be used, and a conductor containingaluminum, a conductor containing copper and titanium, a conductorcontaining copper and manganese, a conductor containing indium, tin, andoxygen, a conductor containing titanium and nitrogen, or the like may beused.

Note that the conductive films 671 b and 672 b may preferably be formedusing a film having a resistance higher than that of the conductivefilms 671 a and 672 a. The conductive films 671 b and 672 b maypreferably be formed using a film having a resistance lower than that ofthe channel of the transistor. For example, the conductive films 671 band 672 b may have a resistivity higher than or equal to 0.1 Ωcm andlower than or equal to 100 Ωcm, higher than or equal to 0.5 Ωcm andlower than or equal to 50 Ωcm, or higher than or equal to 1 Ωcm andlower than or equal to 10 Ωcm. The conductive films 671 b and 672 bhaving a resistivity within the above range can reduce electric fieldconcentration in a boundary portion between the channel and the drain.Therefore, change in electrical characteristics of the transistor can besuppressed. In addition, a punch-through current generated by anelectric field from the drain can be reduced. Thus, a transistor with asmall channel length can have favorable saturation characteristics. Notethat in a circuit configuration where the source and the drain do notinterchange, only one of the conductive films 671 b and 672 b (e.g., thefilm on the drain side) may preferably be provided.

<Structure Example 7 of Transistor>

FIGS. 18A and 18B are a top view and a cross-sectional view of atransistor 680. FIG. 18A is the top view. FIG. 18B illustrates a crosssection along dashed-dotted line A-B in FIG. 18A. In FIGS. 18A and 18B,some components are scaled up or down or omitted for easy understanding.The direction of the dashed-dotted line A-B may be referred to as achannel length direction.

The transistor 680 illustrated in FIG. 18B includes a conductive film689 serving as a first gate, a conductive film 688 serving as a secondgate, a semiconductor 682, a conductive film 683 and a conductive film684 serving as a source and a drain, an insulating film 681, aninsulating film 685, an insulating film 686, and an insulating film 687.

The conductive film 689 is on an insulating surface. The conductive film689 overlaps with the semiconductor 682 with the insulating film 681provided therebetween. The conductive film 688 overlaps with thesemiconductor 682 with the insulating films 685, 686, and 687 providedtherebetween. The conductive films 683 and 684 are connected to thesemiconductor 682.

The description of the conductive films 673 and 674 in FIGS. 11A to 11Dcan be referred to for the details of the conductive films 689 and 688.

The conductive films 689 and 688 may be supplied with differentpotentials, or may be supplied with the same potential at the same time.The conductive film 688 serving as a second gate electrode in thetransistor 680 leads to stabilization of threshold voltage. Note thatthe conductive film 688 is unnecessary in some cases.

The description of the semiconductor 662 in FIGS. 11A to 11D can bereferred to for the details of the semiconductor 682. The semiconductor682 may be a single layer or a stack including a plurality ofsemiconductor layers.

The description of the conductive films 671 and 672 in FIGS. 11A to 11Dcan be referred to for the details of the conductive films 683 and 684.

The description of the insulating film 653 in FIGS. 11A to 11D can bereferred to for the details of the insulating film 681.

The insulating films 685 to 687 are sequentially stacked over thesemiconductor 682 and the conductive films 683 and 684 in FIG. 18B;however, an insulating film provided over the semiconductor 682 and theconductive films 683 and 684 may be a single layer or a stack includinga plurality of insulating films.

In the case of using an oxide semiconductor as the semiconductor 682,the insulating film 686 preferably contains oxygen at a proportionhigher than or equal to that in the stoichiometric composition and has afunction of supplying part of oxygen to the semiconductor 682 byheating. Note that in the case where the provision of the insulatingfilm 686 directly on the semiconductor 682 causes damage to thesemiconductor 682 at the time of formation of the insulating film 686,the insulating film 685 is preferably provided between the semiconductor682 and the insulating film 686, as illustrated in FIG. 18B. Theinsulating film 685 preferably allows oxygen to pass therethrough, andcauses little damage to the semiconductor 682 when the insulating film685 is formed compared with the case of the insulating film 686. Ifdamage to the semiconductor 682 can be reduced and the insulating film686 can be formed directly on the semiconductor 682, the insulating film685 is not necessarily provided.

For the insulating films 686 and 685, a material containing siliconoxide or silicon oxynitride is preferably used, for example.Alternatively, a metal oxide such as aluminum oxide, aluminumoxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttriumoxynitride, hafnium oxide, or hafnium oxynitride can be used.

The insulating film 687 preferably has an effect of blocking diffusionof oxygen, hydrogen, and water. Alternatively, the insulating film 687preferably has an effect of blocking diffusion of hydrogen and water.

As an insulating film has higher density and becomes denser or has afewer dangling bonds and becomes more chemically stable, the insulatingfilm has a more excellent blocking effect. An insulating film that hasan effect of blocking diffusion of oxygen, hydrogen, and water can beformed using, for example, aluminum oxide, aluminum oxynitride, galliumoxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafniumoxide, or hafnium oxynitride. An insulating film that has an effect ofblocking diffusion of hydrogen and water can be formed using, forexample, silicon nitride or silicon nitride oxide.

In the case where the insulating film 687 has an effect of blockingdiffusion of water, hydrogen, and the like, impurities such as water andhydrogen that exist in a resin in a panel or exist outside the panel canbe prevented from entering the semiconductor 682. Since an oxidesemiconductor is used as the semiconductor 682, part of water orhydrogen that enters the oxide semiconductor serves as an electron donor(donor). Thus, the use of the insulating film 687 having the blockingeffect can prevent a shift in the threshold voltage of the transistor680 due to generation of donors.

In addition, since an oxide semiconductor is used as the semiconductor682, when the insulating film 687 has an effect of blocking diffusion ofoxygen, diffusion of oxygen from the oxide semiconductor to the outsidecan be prevented. Accordingly, oxygen vacancies in the oxidesemiconductor that serve as donors are reduced, so that a shift in thethreshold voltage of the transistor 680 due to generation of donors canbe prevented.

Embodiment 5

In this embodiment, a central processing unit (CPU) that includes asemiconductor device or a memory device of one embodiment of the presentinvention will be described.

FIG. 19 is a block diagram illustrating a configuration example of aCPU. The CPU illustrated in FIG. 19 includes, over a substrate 1190, anarithmetic logic unit (ALU) 1191, an ALU controller 1192, an instructiondecoder 1193, an interrupt controller 1194, a timing controller 1195, aregister 1196, a register controller 1197, a bus interface 1198 (BUSI/F), a rewritable ROM 1199, and a ROM interface (ROM I/F) 1189. Asemiconductor substrate, an SOI substrate, a glass substrate, or thelike is used as the substrate 1190. The ROM 1199 and the ROM interface1189 may be provided over a separate chip. Needless to say, the CPU inFIG. 19 is just an example in which the configuration is simplified, andan actual CPU may have a variety of configurations depending on theapplication. For example, the CPU may have the following configuration:a structure including the CPU illustrated in FIG. 19 or an arithmeticcircuit is considered as one core; a plurality of the cores areincluded; and the cores operate in parallel. The number of bits that theCPU can process in an internal arithmetic circuit or in a data bus canbe 8, 16, 32, or 64, for example.

An instruction that is input to the CPU through the bus interface 1198is input to the instruction decoder 1193 and decoded therein, and then,input to the ALU controller 1192, the interrupt controller 1194, theregister controller 1197, and the timing controller 1195.

The ALU controller 1192, the interrupt controller 1194, the registercontroller 1197, and the timing controller 1195 conduct various controlsin accordance with the decoded instruction. Specifically, the ALUcontroller 1192 generates signals for controlling the operation of theALU 1191. While the CPU is executing a program, the interrupt controller1194 judges an interrupt request from an external input/output device ora peripheral circuit on the basis of its priority or a mask state, andprocesses the request. The register controller 1197 generates an addressof the register 1196, and reads/writes data from/to the register 1196 inaccordance with the state of the CPU.

The timing controller 1195 generates signals for controlling operationtimings of the ALU 1191, the ALU controller 1192, the instructiondecoder 1193, the interrupt controller 1194, and the register controller1197. For example, the timing controller 1195 includes an internal clockgenerator for generating an internal clock signal based on a referenceclock signal, and supplies the internal clock signal to the abovecircuits.

In the CPU illustrated in FIG. 19, a memory cell is provided in theregister 1196. For the memory cell of the register 1196, thesemiconductor device or memory device of one embodiment of the presentinvention can be used.

In the CPU illustrated in FIG. 19, the register controller 1197 selectsoperation of retaining data in the register 1196 in accordance with aninstruction from the ALU 1191. That is, the register controller 1197selects whether data is retained by a flip-flop or by a capacitor in thememory cell included in the register 1196. When data retention by theflip-flop is selected, a power supply voltage is supplied to the memorycell in the register 1196. When data retention by the capacitor isselected, the data is rewritten in the capacitor, and supply of thepower supply voltage to the memory cell in the register 1196 can bestopped.

Embodiment 6

The semiconductor device or memory device of one embodiment of thepresent invention can be used for display devices, personal computers,or image reproducing devices provided with recording media (typically,devices which reproduce the content of recording media such as digitalversatile discs (DVDs) and have displays for displaying the reproducedimages). Other examples of electronic devices that can be equipped withthe semiconductor device or memory device of one embodiment of thepresent invention are cellular phones, game machines including portablegame machines, portable data terminals, e-book readers, cameras such asvideo cameras and digital still cameras, goggle-type displays (headmounted displays), navigation systems, audio reproducing devices (e.g.,car audio systems and digital audio players), copiers, facsimiles,printers, multifunction printers, automated teller machines (ATM), andvending machines. FIGS. 20A to 20F illustrate specific examples of theseelectronic devices.

FIG. 20A illustrates a portable game machine, which includes a housing901, a housing 902, a display portion 903, a display portion 904, amicrophone 905, a speaker 906, an operation key 907, a stylus 908, andthe like. Although the portable game machine in FIG. 20A has the twodisplay portions 903 and 904, the number of display portions included ina portable game machine is not limited to this.

FIG. 20B illustrates a cellular phone, which is provided with a housing911, a display portion 916, operation buttons 914, an externalconnection port 913, a speaker 917, a microphone 912, and the like. Whenthe display portion 916 of the cellular phone illustrated in FIG. 20B istouched with a finger or the like, data can be input. Further,operations such as making a call and inputting a character can beperformed by touch on the display portion 916 with a finger or the like.The power can be turned on or off with the operation button 914. Inaddition, types of images displayed on the display portion 916 can beswitched; for example, switching images from a mail creation screen to amain menu screen is performed with the operation button 914.

FIG. 20C illustrates a notebook personal computer, which includes ahousing 921, a display portion 922, a keyboard 923, a pointing device924, and the like.

FIG. 20D illustrates an electric refrigerator-freezer, which includes ahousing 931, a refrigerator door 932, a freezer door 933, and the like.

FIG. 20E illustrates a video camera, which includes a first housing 941,a second housing 942, a display portion 943, operation keys 944, a lens945, a joint 946, and the like. The operation keys 944 and the lens 945are provided in the first housing 941, and the display portion 943 isprovided in the second housing 942. The first housing 941 and the secondhousing 942 are connected to each other with the joint 946, and theangle between the first housing 941 and the second housing 942 can bechanged with the joint 946. Images displayed on the display portion 943may be switched in accordance with the angle at the joint 946 betweenthe first housing 941 and the second housing 942.

FIG. 20F illustrates a car, which includes a car body 951, wheels 952, adashboard 953, lights 954, and the like.

Embodiment 7

In this embodiment, application examples of an RF tag that can be formedusing the semiconductor device or memory device of one embodiment of thepresent invention will be described with reference to FIGS. 21A to 21F.The RF tag is widely used and can be provided for, for example, productssuch as bills, coins, securities, bearer bonds, documents (e.g.,driver's licenses or resident's cards, see FIG. 21A), recording media(e.g., DVDs or video tapes, see FIG. 21B), packaging containers (e.g.,wrapping paper or bottles, see FIG. 21C), vehicles (e.g., bicycles, seeFIG. 21D), personal belongings (e.g., bags or glasses), foods, plants,animals, human bodies, clothing, household goods, medical supplies suchas medicine and chemicals, and electronic devices (e.g., liquid crystaldisplay devices, EL display devices, television sets, or cellularphones), or tags on products (see FIGS. 21E and 21F).

An RF tag 4000 is fixed to a product by being attached to a surfacethereof or embedded therein. For example, the RF tag 4000 is fixed toeach product by being embedded in paper of a book, or embedded in anorganic resin of a package. Since the RF tag 4000 can be reduced insize, thickness, and weight, it can be fixed to a product withoutspoiling the design of the product. Furthermore, bills, coins,securities, bearer bonds, documents, or the like can have anidentification function by being provided with the RF tag 4000, and theidentification function can be utilized to prevent counterfeiting.Moreover, the efficiency of a system such as an inspection system can beimproved by providing the RF tag for packaging containers, recordingmedia, personal belongings, foods, clothing, household goods, electronicdevices, or the like. Vehicles can also have higher security againsttheft or the like by being provided with the RF tag.

As described above, by using the RF tag for each application describedin this embodiment, power for operation such as writing or reading ofdata can be reduced, which results in an increase in the maximumcommunication distance. Moreover, data can be held for an extremely longperiod even in the state where power is not supplied; thus, the RF tagcan be preferably used for application in which data is not frequentlywritten or read.

Next, an application example of a display device that can include thesemiconductor device or memory device of one embodiment of the presentinvention is described. In one example, a display device includes apixel. The pixel includes a transistor and a display element, forexample. Alternatively, the display device includes a driver circuit fordriving the pixel. The driver circuit includes a transistor, forexample. As these transistors, any of the transistors described in theother embodiments can be used, for example.

For example, in this specification and the like, a display element, adisplay device that is a device including a display element, alight-emitting element, and a light-emitting device that is a deviceincluding a light-emitting element can employ a variety of modes or caninclude a variety of elements. A display element, a display device, alight-emitting element, or a light-emitting device includes, forexample, at least one of an electroluminescence (EL) element (e.g., anEL element including organic and inorganic materials, an organic ELelement, or an inorganic EL element), an LED chip (e.g., a white LEDchip, a red LED chip, a green LED chip, or a blue LED chip), atransistor (a transistor that emits light by current), a plasma displaypanel (PDP), an electron emitter, a display element including a carbonnanotube, a liquid crystal element, electronic ink, an electrowettingelement, an electrophoretic element, a display element using microelectro mechanical systems (MEMS) (e.g., grating light valve (GLV), adigital micromirror device (DMD), a digital micro shutter (DMS), MIRASOL(registered trademark), an interferometric modulator display (IMOD)element, a MEMS shutter display element, an optical-interference-typeMEMS display element, and a piezoelectric ceramic display), and quantumdots. Other than the above, the display element, display device,light-emitting element, or light-emitting device may include displaymedia whose contrast, luminance, reflectivity, transmittance, or thelike is changed by electrical or magnetic effect. Examples of displaydevices including EL elements include an EL display. Examples of displaydevices including electron emitters include a field emission display(FED) and an SED-type flat panel display (SED, surface-conductionelectron-emitter display). Examples of display devices including liquidcrystal elements include a liquid crystal display (e.g., a transmissiveliquid crystal display, a transflective liquid crystal display, areflective liquid crystal display, a direct-view liquid crystal display,or a projection liquid crystal display). Examples of a display deviceincluding electronic ink, electronic liquid powder (registeredtrademark), or electrophoretic elements include electronic paper.Examples of display devices including quantum dots in pixels include aquantum dot display. Note that quantum dots may be provided in part of abacklight instead of being used as a display element. The use of quantumdots enables display with high color purity. In the case of atransflective liquid crystal display or a reflective liquid crystaldisplay, some of or all of pixel electrodes function as reflectiveelectrodes. For example, some or all of pixel electrodes are formed tocontain aluminum, silver, or the like. In such a case, a memory circuitsuch as an SRAM can be provided below the reflective electrodes, whichleads to lower power consumption. Note that in the case where an LEDchip is used, graphene or graphite may be provided below an LED chipelectrode or a nitride semiconductor. Graphene or graphite may be amulti-layer film formed by overlap of a plurality of layers. Whengraphene or graphite is provided in this manner, a nitridesemiconductor, for example, an n-type GaN semiconductor layer includingcrystals can be easily formed thereover. The LED chip can be formed byproviding, for example, a p-type GaN semiconductor layer includingcrystals thereover. An AlN layer may be provided between graphene orgraphite and the n-type GaN semiconductor layer including crystals. TheGaN semiconductor layer included in the LED chip may be formed by MOCVD.Note that when graphene is provided, the GaN semiconductor layerincluded in the LED chip can be formed by sputtering. In a displayelement using micro electro mechanical systems (MEMS), a drying agentmay be provided in a space where the display element is sealed (e.g., aspace between an element substrate provided with the display element anda counter substrate facing the element substrate). The drying agent canprevent malfunction and deterioration of the MEMS or the like due tomoisture.

Embodiment 8

In this embodiment, the structure of an oxide semiconductor film thatcan be used for the oxide semiconductor transistor described in theabove embodiment will be described.

In this specification, the term “parallel” indicates that the angleformed between two straight lines is greater than or equal to −10° andless than or equal to 100, and accordingly also includes the case wherethe angle is greater than or equal to −5° and less than or equal to 5°.In addition, the term “substantially parallel” indicates that the angleformed between two straight lines is greater than or equal to −30° andless than or equal to 30°. The term “perpendicular” indicates that theangle formed between two straight lines is greater than or equal to 80°and less than or equal to 1000, and accordingly also includes the casewhere the angle is greater than or equal to 85° and less than or equalto 95°. In addition, the term “substantially perpendicular” indicatesthat the angle formed between two straight lines is greater than orequal to 60° and less than or equal to 120°.

In this specification, trigonal and rhombohedral crystal systems areincluded in a hexagonal crystal system.

An oxide semiconductor film is classified into a single crystal oxidesemiconductor film and a non-single-crystal oxide semiconductor film.Alternatively, an oxide semiconductor is classified into a crystallineoxide semiconductor and an amorphous oxide semiconductor, for example.

Examples of a non-single-crystal oxide semiconductor include a c-axisaligned crystalline oxide semiconductor (CAAC-OS), a polycrystallineoxide semiconductor, a microcrystalline oxide semiconductor, and anamorphous oxide semiconductor. Examples of the crystalline oxidesemiconductor include a single crystal oxide semiconductor, a CAAC-OS, apolycrystalline oxide semiconductor, and a microcrystalline oxidesemiconductor.

First, a CAAC-OS film will be described.

A CAAC-OS film is one of oxide semiconductor films having a plurality ofc-axis aligned crystal parts.

In a combined analysis image (also referred to as a high-resolution TEMimage) of a bright-field image and a diffraction pattern of a CAAC-OSfilm, which is obtained using a transmission electron microscope (TEM),a plurality of crystal parts can be observed. However, in thehigh-resolution TEM image, a boundary between crystal parts, that is, agrain boundary is not clearly observed. Thus, in the CAAC-OS film, areduction in electron mobility due to the grain boundary is less likelyto occur.

According to the high-resolution cross-sectional TEM image of theCAAC-OS film observed in the direction substantially parallel to thesample surface, metal atoms are arranged in a layered manner in thecrystal parts. Each metal atom layer reflects unevenness of a surfaceover which the CAAC-OS film is formed (hereinafter, a surface over whichthe CAAC-OS film is formed is referred to as a formation surface) or thetop surface of the CAAC-OS film, and is arranged parallel to theformation surface or the top surface of the CAAC-OS film.

On the other hand, according to the plan high-resolution TEM image ofthe CAAC-OS film observed in the direction substantially perpendicularto the sample surface, metal atoms are arranged in a triangular orhexagonal arrangement in the crystal parts. However, there is noregularity of arrangement of metal atoms between different crystalparts.

For example, when the structure of a CAAC-OS film including an InGaZnO₄crystal is analyzed by an out-of-plane method using an X-ray diffraction(XRD) apparatus, a peak may appear at a diffraction angle (20) of around31°. This peak is derived from the (009) plane of the InGaZnO₄ crystal,which indicates that crystals in the CAAC-OS film have c-axis alignment,and that the c-axes are aligned in the direction substantiallyperpendicular to the formation surface or the top surface of the CAAC-OSfilm.

Note that in analysis of the CAAC-OS film including an InGaZnO₄ crystalby an out-of-plane method, another peak may appear when 2θ is around360, in addition to the peak at 2θ of around 31°. The peak at 2θ ofaround 36° indicates that a crystal having no c-axis alignment isincluded in part of the CAAC-OS film. It is preferable that in theCAAC-OS film, a peak appear when 2θ is around 31° and that a peak notappear when 2θ is around 36°.

The CAAC-OS film is an oxide semiconductor film with low impurityconcentration. The impurity is an element other than the main componentsof the oxide semiconductor film, such as hydrogen, carbon, silicon, or atransition metal element. In particular, an element (specifically,silicon or the like) having higher strength of bonding to oxygen than ametal element included in an oxide semiconductor film extracts oxygenfrom the oxide semiconductor film, which results in disorder of theatomic arrangement and reduced crystallinity of the oxide semiconductorfilm. Furthermore, a heavy metal such as iron or nickel, argon, carbondioxide, or the like has a large atomic radius (molecular radius), andthus disturbs the atomic arrangement of the oxide semiconductor film andcauses a decrease in crystallinity when it is contained in the oxidesemiconductor film. Note that the impurity contained in the oxidesemiconductor might serve as a carrier trap or a carrier generationsource.

The CAAC-OS film is an oxide semiconductor film having a low density ofdefect states. In some cases, oxygen vacancies in the oxidesemiconductor film serve as carrier traps or serve as carrier generationsources when hydrogen is captured therein, for example.

The state in which impurity concentration is low and density of defectstates is low (the number of oxygen vacancies is small) is referred toas a “highly purified intrinsic” or “substantially highly purifiedintrinsic” state. A highly purified intrinsic or substantially highlypurified intrinsic oxide semiconductor film has few carrier generationsources, and thus can have a low carrier density. Therefore, atransistor including the oxide semiconductor film rarely has negativethreshold voltage (is rarely normally on). The highly purified intrinsicor substantially highly purified intrinsic oxide semiconductor film hasfew carrier traps. Accordingly, the transistor including the oxidesemiconductor film has little variation in electrical characteristicsand high reliability. Electric charge trapped by the carrier traps inthe oxide semiconductor film takes a long time to be released and mightbehave like fixed electric charge. Thus, the transistor including theoxide semiconductor film having high impurity concentration and a highdensity of defect states has unstable electrical characteristics in somecases.

Note that in this specification and the like, the carrier density of asubstantially intrinsic oxide semiconductor film is higher than or equalto 1×10⁻⁹/cm³ and lower than 8×10¹¹/cm³, preferably lower than1×10¹¹/cm³, more preferably lower than 1×10¹⁰/cm³. With a highlypurified intrinsic oxide semiconductor film, the transistor can havestable electric characteristics.

With the use of the CAAC-OS film in a transistor, variation in theelectrical characteristics of the transistor due to irradiation withvisible light or ultraviolet light is small.

Next, a microcrystalline oxide semiconductor will be described.

A microcrystalline oxide semiconductor film has a region in which acrystal part is observed and a region in which a crystal part is notclearly observed in a high-resolution TEM image. In most cases, the sizeof a crystal part included in the microcrystalline oxide semiconductorfilm is greater than or equal to 1 nm and less than or equal to 100 nm,or greater than or equal to 1 nm and less than or equal to 10 nm. Anoxide semiconductor film including a nanocrystal that is a microcrystalwith a size greater than or equal to 1 nm and less than or equal to 10nm, or a size greater than or equal to 1 nm and less than or equal to 3nm is specifically referred to as a nanocrystalline oxide semiconductor(nc-OS) film. In a high-resolution TEM image of the nc-OS film, forexample, a grain boundary is not clearly observed in some cases.

In the nc-OS film, a microscopic region (for example, a region with asize greater than or equal to 1 nm and less than or equal to 10 nm, inparticular, a region with a size greater than or equal to 1 nm and lessthan or equal to 3 nm) has a periodic atomic arrangement. There is noregularity of crystal orientation between different crystal parts in thenc-OS film. Thus, the orientation of the whole film is not ordered.Accordingly, the nc-OS film cannot be distinguished from an amorphousoxide semiconductor film, depending on an analysis method. For example,when the nc-OS film is subjected to structural analysis by anout-of-plane method with an XRD apparatus using an X-ray having adiameter larger than the diameter of a crystal part, a peak which showsa crystal plane does not appear. Furthermore, a diffraction pattern likea halo pattern is observed when the nc-OS film is subjected to electrondiffraction using an electron beam with a probe diameter (e.g., 50 nm orlarger) that is larger than the diameter of a crystal part (the electrondiffraction is also referred to as selected-area electron diffraction).Meanwhile, spots appear in a nanobeam electron diffraction pattern ofthe nc-OS film when an electron beam having a probe diameter close to orsmaller than the diameter of a crystal part is applied. Moreover, in ananobeam electron diffraction pattern of the nc-OS film, regions withhigh luminance in a circular (ring) pattern are shown in some cases.Also in a nanobeam electron diffraction pattern of the nc-OS film, aplurality of spots is shown in a ring-like region in some cases.

The nc-OS film is an oxide semiconductor film that has high regularityas compared with an amorphous oxide semiconductor film. Therefore, thenc-OS film is likely to have a lower density of defect states than anamorphous oxide semiconductor film. Note that there is no regularity ofcrystal orientation between different crystal parts in the nc-OS film.Therefore, the nc-OS film has a higher density of defect states than theCAAC-OS film.

Next, an amorphous oxide semiconductor film will be described.

The amorphous oxide semiconductor film is an oxide semiconductor filmhaving disordered atomic arrangement and no crystal part and exemplifiedby an oxide semiconductor film that exists in an amorphous state, suchas quartz.

In a high-resolution TEM image of the amorphous oxide semiconductorfilm, crystal parts cannot be found.

When the amorphous oxide semiconductor film is subjected to structuralanalysis by an out-of-plane method with an XRD apparatus, a peak thatshows a crystal plane does not appear. A halo pattern is observed whenthe amorphous oxide semiconductor film is subjected to electrondiffraction. Furthermore, a spot is not observed and a halo patternappears when the amorphous oxide semiconductor film is subjected tonanobeam electron diffraction.

Note that an oxide semiconductor film may have a structure havingphysical properties between the nc-OS film and the amorphous oxidesemiconductor film. The oxide semiconductor film having such a structureis specifically referred to as an amorphous-like oxide semiconductor(a-like OS) film.

In a high-resolution TEM image of the a-like OS film, a void may beobserved. Furthermore, in the high-resolution TEM image, there are aregion where a crystal part is clearly observed and a region where acrystal part is not observed. In the a-like OS film, crystallization bya slight amount of electron beam used for TEM observation occurs andgrowth of the crystal part is sometimes found. In contrast, in the nc-OSfilm that has good quality, crystallization hardly occurs by a slightamount of electron beam used for TEM observation.

Note that the crystal part size in the a-like OS film and the nc-OS filmcan be measured using high-resolution TEM images. For example, anInGaZnO₄ crystal has a layered structure in which two Ga—Zn—O layers areincluded between In—O layers. A unit cell of the InGaZnO₄ crystal has astructure in which nine layers including three In—O layers and sixGa—Zn—O layers are stacked in the c-axis direction. Accordingly, thedistance between the adjacent layers is equivalent to the latticespacing on the (009) plane (also referred to as d value). The value iscalculated to be 0.29 nm from crystal structural analysis. Thus,focusing on lattice fringes in the high-resolution TEM image, each oflattice fringes in which the lattice spacing therebetween is greaterthan or equal to 0.28 nm and less than or equal to 0.30 nm correspondsto the a-b plane of the InGaZnO₄ crystal.

Furthermore, the density of an oxide semiconductor film depends on thestructure in some cases. For example, when the composition of an oxidesemiconductor film is determined, the structure of the oxidesemiconductor film can be expected by comparing the density of the oxidesemiconductor film with the density of a single crystal oxidesemiconductor film having the same composition as the oxidesemiconductor film. For example, the density of the a-like OS film ishigher than or equal to 78.6% and lower than 92.3% of the density of thesingle crystal oxide semiconductor film having the same composition. Forexample, the density of each of the nc-OS film and the CAAC-OS film ishigher than or equal to 92.3% and lower than 100% of the density of thesingle crystal oxide semiconductor film having the same composition.Note that it is difficult to deposit an oxide semiconductor film havinga density of lower than 78% of the density of the single crystal oxidesemiconductor film.

Specific examples of the above description will be given. For example,in the case of an oxide semiconductor film having an atomic ratio ofIn:Ga:Zn=1:1:1, the density of single crystal InGaZnO₄ with arhombohedral crystal structure is 6.357 g/cm³. Accordingly, in the caseof the oxide semiconductor film having an atomic ratio ofIn:Ga:Zn=1:1:1, the density of the a-like OS film is higher than orequal to 5.0 g/cm³ and lower than 5.9 g/cm³. For example, in the case ofthe oxide semiconductor film having an atomic ratio of In:Ga:Zn=1:1:1,the density of each of the nc-OS film and the CAAC-OS film is higherthan or equal to 5.9 g/cm³ and lower than 6.3 g/cm³.

Note that there is a possibility that an oxide semiconductor film havinga certain composition cannot exist in a single crystal structure. Inthat case, single crystal oxide semiconductor films with differentcompositions are combined at an adequate ratio, which makes it possibleto calculate density equivalent to that of a single crystal oxidesemiconductor film with the desired composition. The density of a singlecrystal oxide semiconductor film having the desired composition can becalculated using a weighted average according to the combination ratioof the single crystal oxide semiconductor films with differentcompositions. Note that it is preferable to use as few kinds of singlecrystal oxide semiconductor films as possible to calculate the density.

Note that an oxide semiconductor film may be a stack including two ormore of an amorphous oxide semiconductor film, an a-like OS film, amicrocrystalline oxide semiconductor film, and a CAAC-OS film, forexample.

Example 1

As described in the above embodiments, a transistor including an oxidesemiconductor in a channel formation region (hereinafter sometimesreferred to as “OS transistor”) has an extremely low off-state current.In this example, the circuit MC1 shown in FIG. 2 was fabricated toconfirm that the off-state current of the OS transistor is extremely lowand can be expressed by Formula (2) given by the above-mentionedstretched exponential function.

The circuit MC1 shown in FIG. 2 was fabricated and the off-state currentof the transistor M0 was measured by the method described in Embodiment2.

The transistors M1 to M3 and the inverter INV were formed on an SOIsubstrate.

As the transistor M0, the OS transistor illustrated in FIGS. 11A to 11Dwas used.

For the semiconductors 661 to 663 in FIGS. 11A to 11D, oxidesemiconductors formed by a sputtering method were used.

The semiconductor 661 was formed using an In—Ga—Zn oxide with athickness of 40 nm. The semiconductor 661 was formed by a DC sputteringmethod using a target of an In—Ga—Zn oxide containing In, Ga, and Zn atan atomic ratio of 1:3:4. The sputtering method was performed at asubstrate temperature of 200° C. in a mixed gas of argon and oxygen.After the formation of the semiconductor 661, oxygen was introduced intothe semiconductor 661 by an ion implantation method.

The semiconductor 662 was formed using an In—Ga—Zn oxide with athickness of 20 nm. The semiconductor 662 was formed by a DC sputteringmethod using a target of an In—Ga—Zn oxide containing In, Ga, and Zn atan atomic ratio of 1:1:1. The sputtering method was performed at asubstrate temperature of 300° C. in a mixed gas of argon and oxygen. Thesemiconductor 662 was formed using the CAAC-OS film described inEmbodiment 8.

The semiconductor 663 was formed using gallium oxide with a thickness of5 nm. The semiconductor 663 was formed by an RF sputtering method usinga gallium oxide target.

A silicon oxynitride film formed by a PECVD method was used as theinsulating film 652.

A 10-nm-thick silicon oxynitride film was formed as the insulating film653 by a plasma-enhanced CVD (PECVD) method.

After the semiconductors 661 and 662 were formed, heat treatment at 550°C. was performed in a nitrogen atmosphere for one hour and in an oxygenatmosphere for one hour.

The L/W (channel length/channel width) of the transistors M0 to M3 was0.35 μm/0.35 μm.

FIG. 22 shows a cross-sectional scanning transmission electronmicroscope (STEM) image of the prototype circuit MC1. The transistors M1and M2 were formed on the SOI substrate and the transistor M0 was formedabove the transistors M1 and M2.

FIG. 23 shows V_(g)-I_(d) (gate voltage-drain current) characteristicsof a transistor that was fabricated through the same process as thetransistor M0. The transistor whose measurement results are shown inFIG. 23 had L/W of 0.35 μm/0.35 μm, and the drain voltage (V_(ds)) was0.1 V and 1.8 V.

The transistor whose measurement results are shown in FIG. 23 had afield-effect mobility (μ_(FE)) of 2.5 cm²/Vs, a threshold voltage (V_(g)when I_(d)=1 pA) of 0.4 V, and a subthreshold swing of 129 mV/dec.

Next, a voltage drop in the node FN after i-bit data was supplied to thenode FN (data retention characteristics in the node FN) was measured bythe method described in Embodiment 2. Note that in FIG. 2 and FIG. 3,the potentials were set as follows: V_(DD)=1.2 V, V_(ON)=3.3 V,V_(BL)=1.8 V, and V_(SL)=2.6 V. The measurement was performed with thepotential V_(OFF) set to −0.5 V and −1.0 V.

The capacitance of the capacitor Cs was 20 fF, and the measurement wasperformed using SoC Test System (T2000) produced by ADVANTESTCORPORATION.

FIG. 24 shows the results of measuring a voltage drop in the node FNwhen the potential V_(OFF) was −0.5 V. In FIG. 24, the vertical axisrepresents the potential (V_(FN)) of the node FN and the horizontal axisrepresents measurement time (elapsed time after the node FN was broughtinto an electrically floating state). The measurement time was 300seconds and the measurement temperature was 125° C.

It was confirmed that the graph of the potential V_(FN) shown in theFIG. 24 can be approximated by an exponential function represented byFormula (6) below (see the dotted line in the graph). In Formula (6), τis relaxation time and t corresponds to the elapsed time after the nodeFN was brought into an electrically floating state. Formula (6) isequivalent to Formula (2) where β=1.

$\begin{matrix}\left\lbrack {{Formula}\mspace{14mu} 6} \right\rbrack & \; \\{{V_{FN}(t)} = {V_{0} \times e^{- \frac{t}{\tau}}}} & (6)\end{matrix}$

FIG. 25 shows the results of measuring a voltage drop in the node FNwhen the potential V_(OFF) was −1.0 V. As in FIG. 24, the vertical axisrepresents the potential V_(FN) and the horizontal axis representsmeasurement time (elapsed time after the node FN was brought into anelectrically floating state). The measurement time was 216000 secondsand the measurement temperature was 125° C.

In FIG. 25, the solid line shows the results obtained when fitting wasperformed using the stretched exponential function represented byFormula (2), and the dotted line shows the results obtained when fittingwas performed using the exponential function represented by Formula (6).Here, more accurate approximation to the measurement data was achievedwith the stretched exponential function.

FIG. 26 shows the values of τ and β obtained by fitting the potentialV_(FN) with the stretched exponential function represented by Formula(2). The left vertical axis represents τ, the right vertical axisrepresents β, and the horizontal axis represents the potential V_(OFF).The fitting was performed such that the sum of squares of a differencebetween the measurement data and an approximate expression becomesminimum. The measurement was performed on the eight circuits MC1 thatwere formed using one substrate, and their average values are shown inFIG. 26. Note that in FIG. 26, the measurement time was 3600 seconds andthe measurement temperature was 150° C.

A larger τ means a smaller amount of electric charge leaking from thenode FN. In other words, a larger τ means a lower off-state current ofthe transistor M0. In contrast, a smaller τ means a higher off-statecurrent of the transistor M0. As β becomes closer to 1, the potentialV_(FN) can be better expressed using the exponential function. Incontrast, as β becomes closer to 0.5, the potential V_(FN) can be betterexpressed using the stretched exponential function.

From FIG. 26, it can be seen that t increases as the potential V_(OFF)decreases, and τ decreases as the potential V_(OFF) increases.Furthermore, β becomes closer to 1 as the potential V_(OFF) increasesand is approximately 0.5 when the potential V_(OFF) is −1 V or lower.

FIG. 27 shows the off-state current (current I_(OFF)) of the transistorM0 calculated using Formula (5) and τ and β shown in FIG. 26. Thevertical axis represents the current I_(OFF) and the horizontal axisrepresents the potential V_(OFF). From FIG. 27, it can be found that ahigher potential V_(OFF) leads to a higher current I_(OFF) and a lowerpotential V_(OFF) leads to a lower current I_(OFF).

The results in FIG. 26 and FIG. 27 show that τ is large when theoff-state current of the transistor M0 is low, and the potential V_(FN)is preferably approximated by the stretched exponential function. It isalso shown that τ is small when the off-state current of the transistorM0 is high, and the potential V_(FN) is preferably approximated by theexponential function.

As seen from the results in FIG. 26 and FIG. 27, the current I_(OFF) isonly approximately 10⁻²¹ A when the potential V_(OFF) is −1 V or lower.At that time, β is approximately 0.5, and τ is greater than or equal to1×10⁶ seconds and less than or equal to 1×10⁸ seconds.

That is, when the transistor M0 is off and the off-state current is low,β is greater than or equal to 0.3 and less than or equal to 0.7,preferably greater than or equal to 0.4 and less than or equal to 0.6.

In a similar manner, when the transistor M0 is off and the off-statecurrent is low, τ is greater than or equal to 1×10⁶ seconds and lessthan or equal to 1×10⁸ seconds.

FIG. 28 shows an Arrhenius plot of τ that was obtained using thestretched exponential function. In FIG. 28, the potential V_(OFF) is−1.0 V and the measurement time was 1 hour at 150° C., 6 hours at 125°C., and 24 hours at 100° C.

A straight line can be formed by connecting the values as shown in FIG.28, which means that τ follows the Arrhenius equation (Formula (7)). InFormula (7), k is a rate constant, A is a constant independent oftemperatures, E_(a) is activation energy, k_(B) is the Boltzmannconstant, and T is a temperature.

$\begin{matrix}\left\lbrack {{Formula}\mspace{14mu} 7} \right\rbrack & \; \\{k = {A\mspace{11mu} {\exp \left( {- \frac{E_{a}}{k_{B}T}} \right)}}} & (7)\end{matrix}$

From the results in FIG. 28, the activation energy is 1.1 eV.Furthermore, τ extrapolated from the straight line in the graph wasfound to be greater than or equal to 1×10⁷ seconds and less than orequal to 1×10¹⁰ seconds, or greater than or equal to 1×10⁸ seconds andless than or equal to 1×10⁹ seconds at 85° C.

Example 2

In this example, a circuit MC1 was fabricated with the use of thetransistor M0 where L was 100 nm or less to confirm that the off-statecurrent of a minute OS transistor is extremely low and is represented byFormula (2) given by the above-mentioned stretched exponential function.

As in Example 1, the transistors M1 to M3 and the inverter INV wereformed on an SOI substrate.

As the transistor M0, the OS transistor illustrated in FIGS. 11A to 11Dwas used. For the semiconductors 661 to 663 in FIGS. 11A to 11D, oxidesemiconductors formed by a sputtering method were used.

The semiconductor 661 was formed using an In—Ga—Zn oxide with athickness of 20 nm. The semiconductor 661 was formed by a DC sputteringmethod using a target of an In—Ga—Zn oxide containing In, Ga, and Zn atan atomic ratio of 1:3:4. The sputtering method was performed at asubstrate temperature of 200° C. in a mixed gas of argon and oxygen.

The semiconductor 662 was formed using an In—Ga—Zn oxide with athickness of 15 nm. The semiconductor 662 was formed by a DC sputteringmethod using a target of an In—Ga—Zn oxide containing In, Ga, and Zn atan atomic ratio of 1:1:1. The sputtering method was performed at asubstrate temperature of 300° C. in a mixed gas of argon and oxygen. Thesemiconductor 662 was formed using the CAAC-OS film described inEmbodiment 8.

The semiconductor 663 was formed using an In—Ga—Zn oxide with athickness of 5 nm. The semiconductor 663 was formed by a DC sputteringmethod using a target of an In—Ga—Zn oxide containing In, Ga, and Zn atan atomic ratio of 1:3:2. The sputtering method was performed at asubstrate temperature of 200° C. in a mixed gas of argon and oxygen.

A silicon oxynitride film formed by a PECVD method was used as theinsulating film 652. After the insulating film 652 was formed, oxygenwas introduced to the insulating film 652 by an ion implantation method.

A 10-nm-thick silicon oxynitride film was formed as the insulating film653 by a PECVD method.

After the semiconductors 661 and 662 were formed, heat treatment at 450°C. was performed in a nitrogen atmosphere for one hour and in an oxygenatmosphere for one hour.

As in Example 1, the L/W (channel length/channel width) of thetransistors M1 to M3 was 0.35 μm/0.35 μm.

FIGS. 29A and 29B show cross-sectional STEM images of the prototypetransistor M0. FIG. 29A is a cross-sectional image of the transistor M0in the channel width direction, and FIG. 29B is a cross-sectional imageof the transistor M0 in the channel length direction. FIGS. 29A and 29Bshow that a minute transistor whose channel length was approximately 50nm and whose channel width was approximately 30 nm was fabricated.

Similarly to FIG. 25, FIG. 30 shows measurement results of a voltagedrop in the node FN. The measurement was performed on the circuit MC1 inwhich the transistor M0 had a channel length of 50 nm, that in which thetransistor M0 had a channel length of 100 nm, and that in which thetransistor M0 had a channel length of 350 nm. The measurement time was21600 seconds, the measurement temperature was 125° C., and thepotential V_(OFF) was −1.0 V. FIG. 30 also shows measurement data fittedusing the stretched exponential function.

The results in FIG. 30 show that the voltage drop in the node FN followsthe stretched exponential function even when the channel length is 100nm or less. In other words, the off-state current of an OS transistorwhose channel length is 100 nm or less can also be measured using thestretched exponential function.

Example 3

In this example, the OS transistor illustrated in FIGS. 11A to 11D wasfabricated and subjected to a drain bias temperature stress (DBTS) testand off-state current measurement. The prototype OS transistor had highresistance to DBTS and a low off-state current.

In the prototype OS transistor, the semiconductor 661 illustrated inFIGS. 11A to 11D was formed using an In—Ga—Zn oxide with a thickness of40 nm. The semiconductor 661 was formed by a DC sputtering method usinga target of an In—Ga—Zn oxide containing In, Ga, and Zn at an atomicratio of 1:3:4. The sputtering method was performed at a substratetemperature of 200° C. in a mixed gas of argon and oxygen.

The semiconductor 662 was formed using an In—Ga—Zn oxide with athickness of 20 nm. The semiconductor 662 was formed by a DC sputteringmethod using a target of an In—Ga—Zn oxide containing In, Ga, and Zn atan atomic ratio of 1:1:1. The sputtering method was performed at asubstrate temperature of 300° C. in a mixed gas of argon and oxygen. Thesemiconductor 662 was formed using the CAAC-OS film described inEmbodiment 8.

After the semiconductors 661 and 662 were formed, heat treatment at 550°C. was performed in a nitrogen atmosphere for one hour and in an oxygenatmosphere for one hour.

The semiconductor 663 was formed using an In—Ga—Zn oxide with athickness of 5 nm. The semiconductor 663 was formed by a DC sputteringmethod using a target of an In—Ga—Zn oxide containing In, Ga, and Zn atan atomic ratio of 1:3:2. The sputtering method was performed at asubstrate temperature of 200° C. in a mixed gas of argon and oxygen.

For other details about the prototype OS transistor, the description ofthe prototype transistor M0 in Example 1 can be referred to.

FIG. 31 shows the DBTS test results of the prototype OS transistor. FIG.31 shows change in the threshold voltage (ΔV_(th)) of the OS transistorat 150° C. when V_(gs)=0 V and V_(ds)=1.8 V. Furthermore, the L/W of theevaluated OS transistor was 0.18 μm/0.35 μm.

As can be seen in FIG. 31, ΔV_(th) of the prototype OS transistor wasonly approximately −0.01 V to +0.01 V even after 10 hours elapsed.

FIG. 32 shows a cross-sectional STEM image of the prototype OStransistor.

FIG. 33 shows measurement results of the off-state current of theprototype OS transistor. It was observed that the off-state current ofthe OS transistor was as low as 90×10⁻²⁴ A/μm at 85° C.

Example 4

In this example, a memory device including the memory cell 10 a in FIG.6 was fabricated. The data retention characteristics of the prototypememory device were examined to confirm that data can be retained for 10years or longer at 85° C.

FIG. 34 illustrates a device structure of the prototype memory cell 10a. FIG. 34 is a cross-sectional view of the memory cell 10 a for easyunderstanding of the layered structure, the connection, and the like,and is not a cross-sectional view taken along a specific line.

The transistors M1 and M2 are planar transistors and are formed on anSOI semiconductor substrate. Reference numerals 500 and 501 designate asingle crystal silicon wafer and a silicon oxide layer, respectively.Channel regions, source regions, and drain regions of the transistors M1and M2 are in one single crystal silicon layer 520.

The transistor M0 and the capacitor Cs are formed above the transistorsM1 and M2. The prototype memory cell 10 a includes insulating films 502to 511 and seven wiring tiers. The transistors (M0, M1, and M2) and thecapacitor Cs are electrically connected to each other as illustrated inFIG. 6 by conductive layers provided in first to seventh wiring tires.

Conductive layers 531_1 and 531_2 are formed in the first wiring tier.Conductive layers 532_1 to 532_4 are formed in the second wiring tier.Conductive layers 533_1 to 533_5 are formed in the third wiring tier.Conductive layers 534_1 and 534_2 are formed in the fourth wiring tier.Conductive layers 535_1 and 535_2 are formed in the fifth wiring tier.Conductive layers 536_1 to 536_7 are formed in the sixth wiring tier.Conductive layers 537_1 to 537_8 are formed in the seventh wiring tier.The conductive layers 537_1, 537_2, 537_3, 537_4, 537_5, 537_7, and537_8 have portions that serve as wirings WCL, BG, WWL, BL, SL, RWL, andBL, respectively.

In this example, the transistors M1 and M2 were silicon transistors andthe transistor M0 was an OS transistor including a CAAC-OS.

The transistor M0 has a structure similar to that of the OS transistorillustrated in FIGS. 11A to 11D, and has an s-channel structure. Asemiconductor of the transistor M0 consists of three semiconductorlayers 540_1 to 540_3. For details about the semiconductor layers 540_1to 540_3, description of the semiconductors 661 to 663 in Example 1 canbe referred to.

The capacitor Cs is an MIM capacitor and is formed of the conductivelayer 534_2, the semiconductor layer 540_3, the insulating film 507, andthe conductive layer 535_2. The conductive layer 535_2 includes the nodeFN.

The conductive layers 534_1 and 534_2 are each formed of a stackincluding titanium nitride and tungsten. The conductive layers 535_1 and535_2 are each formed using tungsten. The conductive layer 535_2 iselectrically connected to the conductive layer 537_6 through theconductor in the sixth wiring tier (not illustrated). With this wiringstructure, the capacitor Cs is electrically connected to a gateelectrode of the transistor M1.

The insulating film 507 is formed using silicon oxynitride. Theinsulating films 505 and 508 are each aluminum oxide deposited by asputtering method to exhibit a blocking effect against oxygen, hydrogen,water, and the like.

The conductive layer 533_1 overlaps with a channel of the transistor M0and serves as a back gate. The insulating film 504 is formed usingsilicon oxide and the insulating film 505 is formed using siliconoxynitride. The conductive layer 533_1 is electrically connected to theconductive layer 537_2 by conductive layers (not illustrated) in thefifth and sixth wiring tiers.

FIG. 35 is an optical micrograph of the prototype memory device. Thememory device shown in FIG. 35 mainly consists of a controller, a columndriver, a row driver, and a memory cell array.

Table 1 lists the main specifications of the prototype memory device.The memory device has a module size of 1.1×0.5 mm² and a capacity of1040 bits.

TABLE 1 CAAC-OS Technology CAAC-OS FET 0.8 μm memory Si FET 0.35 μmVoltage CAAC-OS FET 3.3 V/−5 V Si FET 1.8 V/1.2 V Module Area 1.1 × 0.5mm² Cell area 8.0 × 8.2 μm² Capacitance 20.6 fF Number of bits 1040 bit

FIG. 36 shows the V_(g)-I_(d) characteristics of the transistor M0 whenthe wiring BG was supplied with −5 V. The drain voltage (V_(ds)) was 0.1V and 1.8 V. In FIG. 36, the characteristics of 25 transistors formed onone substrate are overlaid. From FIG. 36, it was confirmed that theoff-state current of the transistor M0 was lower than or equal to themeasurement limit.

According to the timing chart in FIG. 7, the memory cell 10 a wasoperated to write and read data. In FIG. 7, the potentials were set asfollows: V₁=3.3 V, V₂=1.8 V, V₃=1.2 V, and V_(BG)=−5 V.

Next, the data retention characteristics of the prototype memory devicewere examined. Five memory devices were fabricated and subjected to themeasurement. FIGS. 37A to 37D show the measurement results. Themeasurement was performed at 150° C. (FIG. 37A), 140° C. (FIG. 37B),125° C. (FIG. 37C), and 85° C. (FIG. 37D). The vertical axis of thegraph represents an error ratio (the proportion of defective bits ineach memory device) and the horizontal axis represents measurement time.

In the case where the time until the bit error ratio exceeds 10% (dottedlines in the graphs) is defined as the data retention time, the averagedata retention time was 43 hours at 150° C. In a similar manner, theaverage data retention time was 194 hours at 140° C., 1509 hours at 125°C., and 4000 hours or longer at 85° C.

FIG. 38 shows an Arrhenius plot of the data retention time shown inFIGS. 37A to 37D. A straight line was formed by connecting the averagevalues of the data retention times at the temperatures, which means thatFIG. 38 follows the Arrhenius equation. The data retention time at 85°C. extrapolated from the straight line was calculated to be 138 years.It was confirmed that the prototype memory device can retain data for 10years or longer, or 100 years or longer at 85° C.

As described above, it was found that the memory device of oneembodiment of the present invention can retain data for a long time.

Example 5

In this example, a memory device including the memory cell 10 a in FIG.6 was fabricated using a CAAC-OS transistor that was fabricated usingL=180 nm technology and Si transistors. The data retentioncharacteristics of the prototype memory device were examined to confirmthat data can be retained for 1000 hours or longer at 85° C.

As in Example 4, the memory cell 10 a having the device structureillustrated in FIG. 34 was fabricated.

FIG. 39 shows the V_(g)-I_(d) characteristics of the transistor M0fabricated using L=180 nm technology. The wiring BG was supplied with −5V and V_(ds) was 0.1 V and 1.8 V. In FIG. 39, the characteristics of 25transistors formed on one substrate are overlaid.

FIG. 40 shows measured data retention characteristics of the prototypememory device in this example. The measurement was performed at 85° C.When the time until the bit error ratio exceeds 10% is defined as thedata retention time as in the case of FIGS. 37A to 37D, the dataretention time of the prototype memory device in this example was foundto be 1000 hours or longer.

As described above, it was found that the memory device of oneembodiment of the present invention can retain data for a long time.

Example 6

In this example, variation in electrical characteristics of thetransistors M0 in a memory device including the memory cells 10 aillustrated in FIG. 6 was examined.

FIG. 41A is a circuit diagram of a test element group (TEG) fabricatedfor examining variation in electrical characteristics of the transistorsM0. A cell 11 in FIG. 41A is the memory cell 10 a in FIG. 6 which is notprovided with the transistors M1 and M2 and the wiring RWL and in whichone of the source and the drain of the transistor M0 and the firstterminal of the capacitor Cs are connected to the wiring SL.

The cell 11 has a function of writing electric charge from the wiring BLto the capacitor Cs and the wiring SL through the transistor M0.

FIG. 41B is a timing chart of operation of the cell 11. First, thewiring BL is supplied with the potential BL. Then, the wiring SL isbrought into an electrically floating state, and then, the wiring WWL issupplied with an H level (potential V_(WL)), whereby the transistor M0is turned on. As a result, the capacitor Cs and the wiring SL arecharged from the wiring BL through the transistor M0, so that thepotential of the wiring SL increases. After 15 microseconds from thestart of the charging, the potential V_(SL) of the wiring SL is read,whereby the characteristics of the transistor M0 can be examined. Notethat the wiring WCL and the wiring BG are constantly supplied with thepotential GND.

In the cell 11, the characteristics to be examined depend on the levelof the potential V_(WL) supplied to the wiring WWL. In the case wherethe potential V_(WL) is lower than the sum of the potential V_(BL) andV_(th) (the threshold voltage of the transistor M0), i.e.,V_(WL)<V_(BL)+V_(th), the potential V_(SL) is substantially equal to avalue obtained by subtracting V_(th) from the potential V_(WL); thus, bymeasuring the potential V_(SL), the characteristics associated with thethreshold voltage of the transistor M0 are determined.

In the case where the potential V_(WL) is higher than the sum of thepotential V_(BL) and V_(th), i.e., V_(WL)>V_(BL)+V_(th), the potentialV_(SL) is substantially equal to a value obtained by subtracting ΔV_(OS)(a voltage drop due to on-state resistance of the transistor M0) fromthe potential V_(WL), thus, by measuring the potential V_(SL), thecharacteristics associated with the on-state resistance of thetransistor M0 are determined. Note that on-state resistance isresistance generated between the source and the drain when thetransistor M0 is turned on.

FIG. 41C is a circuit diagram of the cell array 20 including the cells11. In the cell array 20, the cells 11 are arranged in a matrix of 512rows and 64 columns, and all the wirings SL are connected to a circuit30 (FIG. 41C). The circuit 30 includes a voltage follower circuit andhas a function of reading the potentials V_(SL) output from the 32768(512×64) cells 11 sequentially.

In this example, the memory device shown in FIG. 47 was fabricated. FIG.47 is a photograph showing the appearance of a chip including theprototype memory device. The cell array 20 in FIG. 41C was provided inthe cell array of the prototype chip.

As illustrated in FIG. 34, the transistor M0 and the capacitor Cs wereformed above the transistors M1 and M2 formed on the SOI substrate. Asthe transistor M0, the OS transistor illustrated in FIGS. 11A to 11D wasused.

The semiconductor 661 was formed using an In—Ga—Zn oxide with athickness of 40 nm. The semiconductor 661 was formed by a DC sputteringmethod using a target of an In—Ga—Zn oxide containing In, Ga, and Zn atan atomic ratio of 1:3:4. The sputtering method was performed at asubstrate temperature of 200° C. in a mixed gas of argon and oxygen.

The semiconductor 662 was formed using an In—Ga—Zn oxide with athickness of 20 nm. The semiconductor 662 was formed by a DC sputteringmethod using a target of an In—Ga—Zn oxide containing In, Ga, and Zn atan atomic ratio of 1:1:1. The sputtering method was performed at asubstrate temperature of 300° C. in a mixed gas of argon and oxygen. Thesemiconductor 662 was formed using the CAAC-OS film described inEmbodiment 8.

The semiconductor 663 was formed using an In—Ga—Zn oxide with athickness of 5 nm. The semiconductor 663 was formed by a DC sputteringmethod using a target of an In—Ga—Zn oxide containing In, Ga, and Zn atan atomic ratio of 1:3:2. The sputtering method was performed at asubstrate temperature of 200° C. in a mixed gas of argon and oxygen.

A silicon oxynitride film formed by a PECVD method was used as theinsulating film 652.

A 10-nm-thick silicon oxynitride film was formed as the insulating film653 by a PECVD method.

The insulating film 654 was formed using 140-nm-thick aluminum oxide.The insulating film 654 was formed by an RF sputtering method performedin a mixed gas of argon and oxygen using a target of aluminum oxide.

The L/W of the transistor M0 was 0.18 μm/0.35 μm.

Measurement was performed on the 32768 cells 11 in FIG. 41C. FIGS. 42Aand 42B show histograms of the potential V_(SL) obtained by themeasurement In the measurement, the potential V_(BL) and the potentialV_(WL) were 1.8 V. The vertical axis in FIG. 42A is on a linear scale,and the vertical axis in FIG. 42B is on a logarithmic scale. The dottedlines in the graphs are normal distribution curves obtained by fittingthe measurement results with a probability density function.

The results in FIGS. 42A and 42B show that variation in the potentialV_(SL) is 3 σ=72 mV.

Similarly to FIG. 42A, FIG. 43 shows histograms of the potential V_(SL)of the cells 11 that are illustrated in FIG. 41C. In FIG. 43, thepotential V_(BL) was 1.8 V and the potential V_(WL) was varied from 1.0V to 2.9 V in increments of 0.1 V.

The histograms in FIG. 43 show that the potential V_(SL) has a normaldistribution in all the measurements except for that when V_(WL)=1.0 Vin which case the circuit 30 does not operate. Specifically, when thepotential V_(WL) was 1.1 V, variation in the potential V_(SL) was assmall as 30=49.1 mV.

FIG. 44A shows 3σ of the potential V_(SL) that was obtained from thehistograms in FIG. 43 as a function of the potential V_(WL). In asimilar manner, FIG. 44B shows the average value of the potential V_(SL)(the median of a normal distribution curve) that was obtained from thehistograms in FIG. 43 as a function of the potential V_(WL).

The results in FIG. 44A show that 3σ of the potential V_(SL) graduallyincreases with the increasing potential V_(WL) and has a local maximumvalue (3σ=82.5 mV) when the potential V_(WL) is 2.5 V. As describedabove, a cause of a variation in the electrical characteristics of thetransistors M0 depends on the value of the potential V_(WL). From FIG.44A, the variation in the electrical characteristics of the transistorsM0 is found to be more affected by the on-state resistance of thetransistor M0 than by the threshold voltage of the transistor M0.

The results in FIG. 44B show a gradual increase in the average value ofthe potential V_(SL) that accompanies the increase in potential V_(WL).The potential V_(WL) also affects the average value of the potentialV_(SL), which means that the results in FIG. 43 reflect the switchingcharacteristics of the transistor M0.

The prototype memory device in this example includes eight cell arrays20 in each chip. Furthermore, in this example, the memory device wasfabricated in such a manner that a plurality of chips can be cut out ofone substrate. FIGS. 45A and 45B show measurement results of 3σ of thepotential V_(SL) for the eight cell arrays 20 included in each of eightchips formed on one substrate (chips A to H), i.e., for the 8×8=64 cellarrays 20 formed on one substrate. In the measurement, the potentialV_(BL) and the potential V_(WL) were 1.8 V. Note that data on one cellarray 20 included in the chip A was not obtained owing to malfunction ofthe circuit 30.

From the results in FIGS. 45A and 45B, it was confirmed that thevariation in the potential V_(SL) was between 30-50 mV and approximately3σ=80 mV in any chip or any cell array 20.

FIG. 46 shows a histogram of the potential V_(SL) in the case wheremeasurement was performed on 512 cells 11 connected to one wiring BL(see FIG. 41C). In the measurement, the potential V_(BL) and thepotential V_(WL) were 1.8 V. It was found from FIG. 46 that variation inthe potential V_(SL) due to the transistors M0 arranged in the columndirection is 3σ=43.8 mV (50 mV or lower).

Example 7

In this example, a memory device including the memory cell 10 a in FIG.6 was fabricated using a CAAC-OS transistor that was fabricated usingL=180 nm technology and Si transistors, and the data retentioncharacteristics thereof were examined.

As illustrated in FIG. 34, the transistor M0 was formed above thetransistors M1 and M2 formed on the SOI substrate. As the transistor M0,the OS transistor illustrated in FIGS. 11A to 11D was used.

A 10-nm-thick silicon oxynitride film formed by a PECVD method was usedas the insulating film 651 in FIGS. 11A to 11D. A 20-nm-thick hafniumoxide film formed by an atomic layer deposition (ALD) method was used asthe insulating film 656. A 30-nm-thick silicon oxynitride film formed bya PECVD method was used as the insulating film 652. Note that theinsulating film 656 serves as a charge trap layer.

The semiconductor 661 was formed using an In—Ga—Zn oxide with athickness of 40 nm. The semiconductor 661 was formed by a DC sputteringmethod using a target of an In—Ga—Zn oxide containing In, Ga, and Zn atan atomic ratio of 1:3:4. The sputtering method was performed at asubstrate temperature of 200° C. in a mixed gas of argon and oxygen.After the formation of the semiconductor 661, oxygen was introduced intothe semiconductor 661 by an ion implantation method.

The semiconductor 662 was formed using an In—Ga—Zn oxide with athickness of 20 nm. The semiconductor 662 was formed by a DC sputteringmethod using a target of an In—Ga—Zn oxide containing In, Ga, and Zn atan atomic ratio of 1:1:1. The sputtering method was performed at asubstrate temperature of 300° C. in a mixed gas of argon and oxygen. Thesemiconductor 662 was formed using the CAAC-OS film described inEmbodiment 8.

After the semiconductors 661 and 662 were formed, heat treatment at 550°C. was performed in a nitrogen atmosphere for one hour and in an oxygenatmosphere for one hour.

The semiconductor 663 was formed using an In—Ga—Zn oxide with athickness of 5 nm. The semiconductor 663 was formed by a DC sputteringmethod using a target of an In—Ga—Zn oxide containing In, Ga, and Zn atan atomic ratio of 1:3:2. The sputtering method was performed at asubstrate temperature of 200° C. in a mixed gas of argon and oxygen.

A 13-nm-thick silicon oxynitride film was formed as the insulating film653 by a PECVD method.

The insulating film 654 was formed using 140-nm-thick aluminum oxide.The insulating film 654 was formed by an RF sputtering method performedin a mixed gas of argon and oxygen using a target of aluminum oxide.

To control the threshold voltage of the transistor M0, a voltage of 38 Vwas applied to the conductive film 674 for three seconds and electriccharges were injected into the insulating film 656.

Data was written in the node FN of the memory cell 10 a, and thepotential V_(FN) of the node FN immediately after the writing wasmeasured. The data writing in the node FN was performed by supplying thewiring WWL with a potential V_(WL) of 3.3 V, supplying the wiring BLwith a potential V_(BL) of 1.8 V (writing data “1”) or a potentialV_(BL) of 0 V (writing data “0”), and supplying the wiring WCL with 0 Vor 1.2 V.

Data writing was performed in the memory cell array including the 1040memory cells 10 a. FIG. 48 shows a histogram of the potential V_(FN)immediately after the writing.

In FIG. 48, the horizontal axis represents the potential V_(FN) and thevertical axis represents the number of the memory cells 10 a in whichthe potential V_(FN) corresponding to the horizontal axis was written.From FIG. 48, both the histogram in the case where data “1” was writtenand that in the case where data “0” was written were found to have anormal distribution.

Next, after the data writing in the 1040 memory cells 10 a, thetemperature of the measurement environment was set at 150° C., and thepotential V_(FN) was measured in the state where the potential V_(WL),the potential V_(BL), and the potential V_(BG) (the potential of thewiring BG) were 0 V. The measurement was performed until 322 hourselapsed since data was written in the memory cell 10 a. FIGS. 49A and49B, FIG. 50, and FIGS. 51A to 51C show the measurement results.

FIGS. 49A and 49B each show a bit error ratio as a function ofmeasurement time in the memory cell 10 a. Note that in FIGS. 49A and49B, the time immediately after data writing is denoted as “ini.” Ineach of FIG. 49A (data “0”) and FIG. 49B (data “0”), all of the 1040memory cells 10 a were found to retain data for 322 hours at 150° C.

FIG. 50 shows histograms of the potential V_(FN) after 0 hours, 113hours, and 332 hours in the measurement in FIGS. 49A and 49B. In thecase of data “1,” the median of the histogram was observed to shift tothe low voltage side with the passage of measurement time. However, thewidth of the histogram (variation in potential V_(FN)) was not changed.

FIGS. 51A to 51C are histograms of the potentials V_(FN) of three memorycell arrays, which are different from the above-mentioned memory cellarray. The histograms in FIG. 50 and FIGS. 51A to 51C show themeasurement results of the memory cell arrays formed at the respectivepositions of one substrate. For the measurement conditions of FIGS. 51Ato 51C, the description of FIG. 50 can be referred to. FIG. 50 and FIGS.51A to 51C show that similar measurement results are obtained from thememory cell arrays formed on one substrate. It was found that in thecase of data “1,” the potential V_(FN) is most likely to varyimmediately after the start of the measurement and is unlikely to varyafter certain time. In the case of data “0,” no great change in thehistogram due to passage of measurement time was observed.

FIG. 52 shows a histogram of the potential V_(FN) in the case where thetemperature of the measurement environment was 60° C. The measurementwas performed until 369 hours elapsed since data was written in thememory cell 10 a. For other measurement conditions, the abovedescription of measurement conditions can be referred to. Note that thetemperature of 60° C. is close to the temperature of the environment inwhich the memory cell 10 a is actually used.

From the results in FIG. 52, it was found that the memory cell 10 ashows no change in the potential written in the node FN for 369 hours at60° C.

FIG. 53 shows histograms of the potential V_(FN) in the case where thetemperature of the measurement environment was room temperature (RT),60° C., 85° C., 100° C., 125° C., and 150° C. For other measurementconditions, the above description of measurement conditions can bereferred to. FIG. 53 shows the histograms after 0 hours elapsed afterthe data writing in the memory cell 10 a and those after 200 hourselapsed after the data writing in the memory cell 10 a.

As can be seen from the results in FIG. 53, the histogram in the case ofdata “0” was hardly observed to change at all the temperatures. In thecase of data “1,” the median of the histogram was observed to shift tothe low voltage side as the temperature became high.

This application is based on Japanese Patent Application serial no.2015-017746 filed with Japan Patent Office on Jan. 30, 2015, JapanesePatent Application serial no. 2015-044801 filed with Japan Patent Officeon Mar. 6, 2015, and Japanese Patent Application serial no. 2015-054916filed with Japan Patent Office on Mar. 18, 2015, the entire contents ofwhich are hereby incorporated by reference.

1. (canceled)
 2. A semiconductor device comprising: a memory cell; andan inverter, wherein the memory cell comprises: a first transistor; asecond transistor; and a capacitor, wherein the first transistorcomprises an oxide semiconductor in a channel formation region, whereina gate of the second transistor and a first terminal of the capacitorare electrically connected to a node, wherein one of a source and adrain of the second transistor is electrically connected to an inputterminal of the inverter, wherein an output terminal of the inverter iselectrically connected to an output terminal, wherein the node isconfigured to be supplied with a potential V₀ through the firsttransistor, wherein the node is configured to be brought into anelectrically floating state by turning off the first transistor afterthe potential V₀ is supplied, and wherein change in a potential V_(FN)of the node with respect to time is expressed by Formula (1):$\begin{matrix}{{{V_{FN}(t)} = {V_{0} \times e^{- {(\frac{t}{\tau})}^{\beta}}}},} & (1)\end{matrix}$ where t is elapsed time after the node is brought into theelectrically floating state, τ is a constant with a unit of time, and βis a constant greater than or equal to 0.4 and less than or equal to0.6.
 3. The semiconductor device according to claim 1, furthercomprising: a third transistor, wherein one of a source and a drain ofthe third transistor is electrically connected to the one of the sourceand the drain of the second transistor.
 4. The semiconductor deviceaccording to claim 1, wherein the τ follows the Arrhenius equation. 5.The semiconductor device according to claim 1, wherein an off-statecurrent of the first transistor is obtained by measuring the change inthe potential V_(FN) over time.
 6. The semiconductor device according toclaim 1, wherein data is retained for 10 years or longer at 85° C.
 7. Asemiconductor device comprising: a memory cell; and an inverter, whereinthe memory cell comprises: a first transistor; a second transistor; anda capacitor, wherein the first transistor comprises a stack of oxidesemiconductor layers in a channel formation region, wherein a gate ofthe second transistor and a first terminal of the capacitor areelectrically connected to a node, wherein one of a source and a drain ofthe second transistor is electrically connected to an input terminal ofthe inverter, wherein an output terminal of the inverter is electricallyconnected to an output terminal, wherein the node is configured to besupplied with a potential V₀ through the first transistor, wherein thenode is configured to be brought into an electrically floating state byturning off the first transistor after the potential V₀ is supplied,wherein change in a potential V_(FN) of the node with respect to time isexpressed by Formula (1): $\begin{matrix}{{{V_{FN}(t)} = {V_{0} \times e^{- {(\frac{t}{\tau})}^{\beta}}}},} & (1)\end{matrix}$ where t is elapsed time after the node is brought into theelectrically floating state, τ is a constant with a unit of time, and βis a constant greater than or equal to 0.4 and less than or equal to0.6, and wherein the stack of the oxide semiconductor layers comprises afirst oxide semiconductor layer, a second oxide semiconductor layer overthe first oxide semiconductor layer, and a third oxide semiconductorlayer over the second oxide semiconductor layer.
 8. The semiconductordevice according to claim 7, further comprising: a third transistor,wherein one of a source and a drain of the third transistor iselectrically connected to the one of the source and the drain of thesecond transistor.
 9. The semiconductor device according to claim 7,wherein the τ follows the Arrhenius equation.
 10. The semiconductordevice according to claim 7, wherein an off-state current of the firsttransistor is obtained by measuring the change in the potential V_(FN)over time.
 11. The semiconductor device according to claim 7, whereindata is retained for 10 years or longer at 85° C.
 12. An electronicdevice comprising: the semiconductor device according to claim 7; and atleast one of a microphone, a speaker, a display portion, and anoperation key.